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https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk
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[/] [riscv_vhdl/] [trunk/] [examples/] [dhrystone21/] [makefiles/] [test_riscv.ld] - Rev 5
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OUTPUT_ARCH( "riscv" )
/*----------------------------------------------------------------------*/
/* Sections */
/*----------------------------------------------------------------------*/
SECTIONS
{
/* text: test code section */
. = 0x10000000;
.text :
{
*(.text.entrypoint*)
*(.text*)
}
/* data segment */
.data : { *(.data) }
.sdata : {
*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)
*(.sdata .sdata.* .gnu.linkonce.s.*)
}
/* bss segment */
.sbss : {
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
}
.bss : { *(.bss) }
/* thread-local data segment */
.tdata :
{
*(.tdata)
}
.tbss :
{
*(.tbss)
}
/* End of uninitalized data segement */
_end = .;
}