Subversion Repositories riscv_vhdl

git submodule foreach git pull origin master
make CONFIG=GnssConfig verilog
ModelSim: Global define for behav.srams.v +define+RANDOMIZE=1
ModelSim: Global define for rocketchip.GnssConfig.v +define+RANDOMIZE_REG_INIT=1

// VCD stimulus in ModelSim from SystemC.
// ModelSim uses only 1-bit signals, so convert VCD -> WLF -> VCD.
vcd2wlf E:/Projects/GitProjects/riscv_vhdl/debugger/win32build/Debug/intdiv.vcd -o e:/indiv.wlf
wlf2vcd e:/indiv.wlf -o e:/intdiv.vcd
vsim -t 1ps -vcdstim E:/intdiv.vcd riverlib.intdiv -do "add wave sim:/intdiv/*; run 10000000"
vsim -view e:/indiv.wlf  -- Add wlf-data to wave-viewer.
add wave o_fetch:/SystemC/*
// Comparision
compare start o_mem sim
compare add -wave sim:/memaccess/o_mem_addr
compare run
compare end

//////////////////////////////
// SCALA modifications
rocketchip/Configs.scals
+class GnssConfig extends Config(new BaseConfig)

/* @brief: Enable rwx permssions and make cachable < 0x80000000
 *
 * This must enable rwx permissions for all memory regions
 */
//Check that build output memory mapping contains Debug regions
        0x0 - 0x1000 Debug rwx
//Let's fake all memories will be mapped to this region manager
rocket/TLB.scala
  val prot_r = fastCheck(_.supportsGet)     !!! fastCheck need to change
  val prot_w = fastCheck(_.supportsPutFull)
  val prot_x = fastCheck(_.executable)
-+  val cacheable = ~mpu_physaddr(31)//fastCheck(_.supportsAcquire)
uncore/tilelink2/parameters.scala
-  def find(address: BigInt) = managers.find(_.address.exists(_.contains(address)))
+  def find(address: BigInt) = managers.find(_.address.exists(_.contains(BigInt(0x0))))

  // The safe version will check the entire address
-  def findSafe(address: UInt) = Vec(managers.map(_.address.map(_.contains(address)).reduce(_ || _)))
+  def findSafe(address: UInt) = Vec(managers.map(_.address.map(_.contains(UInt(0x0))).reduce(_ || _)))
  // The fast version assumes the address is valid
-  def findFast(address: UInt) = Vec(managers.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
+  def findFast(address: UInt) = Vec(managers.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(UInt(0x0))).reduce(_ || _)))


////////////////////////////
// Generated Verilog fixes
// Use search [0:127] !!;
module BTB add reset:
    if(reset) begin
`ifndef SYNTHESIS
      for (initvar=0; initvar<128; initvar=initvar+1) begin 
        _T_2578[initvar] <= 2'b00;
      end
`endif
    end else if(T_2209_T_2234_en & T_2209_T_2234_mask) begin
      _T_2578[T_2209_T_2234_addr] <= T_2209_T_2234_data;
    end


CSRFile:: reset "reg_mideleg" and "reg_medeleg"                           b
    if(reset) begin
      reg_mideleg <= 64'd0;
    end else begin
      if(wen) begin
        if(T_6079) begin
          reg_mideleg <= T_7516;
        end
      end
    end
    if(reset) begin
      reg_medeleg <= 64'd0;
    end else begin
      if(wen) begin
        if(T_6081) begin
          reg_medeleg <= T_7517;
        end
      end
    end


/* @brief how to find registers info
 *
 * Find the following code in module Rocket(..)
 */
`ifdef PRINTF_COND
    if (`PRINTF_COND) begin
`endif
    if (T_8604) begin
        $fwrite(32'h80000002,"C%d: %d [%d] pc=[%h] W[r%d=%h][%d] R[r%d=%h] R[r%d=%h] inst=[%h] DASM(%h)\n",\
        io_hartid, - core
        T_8594,    - csr_io_time
        wb_valid,
        wb_reg_pc, - pc
        T_8596,    - register write idx r0..r31
        rf_wdata,  - new value
        rf_wen,    - 
        T_8597,    - register read1 idx
        T_8599,    - read1 value
        T_8600,    - register read2 idx
        T_8602,    - read2 value
        wb_reg_inst, - inst
        wb_reg_inst);
    end
`ifdef PRINTF_COND



---------------------------------------------
HOW TO build toolchain for soft-float?
---------------------------------------------
cd riscv-tools/riscv-gnu-toolchain
./configure --prefix=/home/teeshina/riscv/gcc-softloat --disable-float
mkdir /home/teeshina/riscv/gcc-softloat
export PATH=/home/teeshina/riscv/gcc-softloat/bin:$PATH
make