Subversion Repositories riscv_vhdl

Entering 'chisel'
Entering 'context-dependent-environments'
Entering 'dramsim2'
Entering 'fpga-zynq'
Entering 'groundtest'
Entering 'hardfloat'
Entering 'junctions'
Entering 'riscv-tools'
Entering 'riscv-tools/riscv-tests'
Entering 'riscv-tools/riscv-tests/env'
Entering 'rocket'
diff --git a/src/main/scala/csr.scala b/src/main/scala/csr.scala
index 62f81ff..ae649b0 100644
--- a/src/main/scala/csr.scala
+++ b/src/main/scala/csr.scala
@@ -155,9 +155,9 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
   val system_insn = io.rw.cmd === CSR.I
   val cpu_ren = io.rw.cmd =/= CSR.N && !system_insn
 
-  val host_csr_req_valid = Reg(Bool()) // don't reset
+  val host_csr_req_valid = Reg(init=Bool(false)) // don't reset
   val host_csr_req_fire = host_csr_req_valid && !cpu_ren
-  val host_csr_rep_valid = Reg(Bool()) // don't reset
+  val host_csr_rep_valid = Reg(init=Bool(false)) // don't reset
   val host_csr_bits = Reg(io.host.csr.req.bits)
   io.host.csr.req.ready := !host_csr_req_valid && !host_csr_rep_valid
   io.host.csr.resp.valid := host_csr_rep_valid
diff --git a/src/main/scala/nbdcache.scala b/src/main/scala/nbdcache.scala
index 2d0eee2..a2d8bbe 100644
--- a/src/main/scala/nbdcache.scala
+++ b/src/main/scala/nbdcache.scala
@@ -395,7 +395,8 @@ class MSHRFile(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   }
 
   // determine if the request is in the memory region or mmio region
-  val cacheable = io.req.bits.addr < UInt(mmioBase)
+  //val cacheable = io.req.bits.addr < UInt(mmioBase)
+  val cacheable = Bool(false)
 
   val sdq_val = Reg(init=Bits(0, sdqDepth))
   val sdq_alloc_id = PriorityEncoder(~sdq_val(sdqDepth-1,0))
diff --git a/src/main/scala/rocket.scala b/src/main/scala/rocket.scala
index d965709..dfdf549 100644
--- a/src/main/scala/rocket.scala
+++ b/src/main/scala/rocket.scala
@@ -163,6 +163,10 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
   val wb_reg_wdata = Reg(Bits())
   val wb_reg_rs2 = Reg(Bits())
   val take_pc_wb = Wire(Bool())
+  //SH
+  val reg_ll_wdata_postponed = Reg(Bits())
+  val reg_ll_waddr_postponed = Reg(Bits())
+  val reg_ll_wen_postponed = Reg(init = Bool(false))
 
   val take_pc_mem_wb = take_pc_wb || take_pc_mem
   val take_pc = take_pc_mem_wb
@@ -410,12 +414,36 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
 
   val wb_valid = wb_reg_valid && !replay_wb && !csr.io.csr_xcpt
   val wb_wen = wb_valid && wb_ctrl.wxd
-  val rf_wen = wb_wen || ll_wen 
-  val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr)
+
+  //SH
+  val stall_wen = ll_wen && wb_wen// && (wb_waddr === UInt(0x1))
+  when (stall_wen) {
+       reg_ll_wen_postponed := Bool(true)
+       reg_ll_waddr_postponed := wb_waddr
+       reg_ll_wdata_postponed := wb_reg_wdata
+  }
+  when (!wb_wen || (!ll_wen && wb_wen && wb_waddr === reg_ll_waddr_postponed)) {
+       reg_ll_wen_postponed := Bool(false)
+       reg_ll_waddr_postponed := UInt(0)
+       reg_ll_wdata_postponed := UInt(0)
+  }
+  val rf_wen = wb_wen || ll_wen || reg_ll_wen_postponed
+  val rf_waddr = Mux(ll_wen, ll_waddr, 
+                 Mux(wb_wen, wb_waddr, 
+                 reg_ll_waddr_postponed))
+
   val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data,
                  Mux(ll_wen, ll_wdata,
                  Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata,
-                 wb_reg_wdata)))
+                 Mux(wb_wen, wb_reg_wdata,
+                 reg_ll_wdata_postponed))))
+
+  //val rf_wen = wb_wen || ll_wen 
+  //val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr)
+  //val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data,
+  //               Mux(ll_wen, ll_wdata,
+  //               Mux(wb_ctrl.csr != CSR.N, csr.io.rw.rdata,
+  //               wb_reg_wdata)))
   when (rf_wen) { rf.write(rf_waddr, rf_wdata) }
 
   // hook up control/status regfile
@@ -484,7 +512,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
     id_ctrl.mem && !io.dmem.req.ready ||
     Bool(usingRoCC) && wb_reg_rocc_pending && id_ctrl.rocc && !io.rocc.cmd.ready ||
     id_do_fence ||
-    csr.io.csr_stall
+    csr.io.csr_stall || 
+    stall_wen || reg_ll_wen_postponed   //SH
   ctrl_killd := !io.imem.resp.valid || take_pc || ctrl_stalld || csr.io.interrupt
 
   io.imem.req.valid := take_pc
diff --git a/src/main/scala/tlb.scala b/src/main/scala/tlb.scala
index 55e7359..5ff3fda 100644
--- a/src/main/scala/tlb.scala
+++ b/src/main/scala/tlb.scala
@@ -148,14 +148,10 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
     plru.access(OHToUInt(tag_cam.io.hits))
   }
 
-  val paddr = Cat(io.resp.ppn, UInt(0, pgIdxBits))
-  val addr_ok = addrMap.isValid(paddr)
-  val addr_prot = addrMap.getProt(paddr)
-
   io.req.ready := state === s_ready
-  io.resp.xcpt_ld := !addr_ok || !addr_prot.r || bad_va || tlb_hit && !(r_array & tag_cam.io.hits).orR
-  io.resp.xcpt_st := !addr_ok || !addr_prot.w || bad_va || tlb_hit && !(w_array & tag_cam.io.hits).orR
-  io.resp.xcpt_if := !addr_ok || !addr_prot.x || bad_va || tlb_hit && !(x_array & tag_cam.io.hits).orR
+  io.resp.xcpt_ld := bad_va || tlb_hit && !(r_array & tag_cam.io.hits).orR
+  io.resp.xcpt_st := bad_va || tlb_hit && !(w_array & tag_cam.io.hits).orR
+  io.resp.xcpt_if := bad_va || tlb_hit && !(x_array & tag_cam.io.hits).orR
   io.resp.miss := tlb_miss
   io.resp.ppn := Mux(vm_enabled, Mux1H(tag_cam.io.hits, tag_ram), io.req.bits.vpn(ppnBits-1,0))
   io.resp.hit_idx := tag_cam.io.hits
Entering 'torture'
Entering 'uncore'
Entering 'zscale'