OpenCores

URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [rtl/] [prj/] [modelsim/] [.gitignore] - Rev 5

Compare with Previous | Blame | View Log

*.wlf
*.mti
*.do
ambalib/*
!ambalib/_info
commonlib/*
!commonlib/_info
gnsslib/*
!gnsslib/_info
rocketlib/*
!rocketlib/_info
riverlib/*
!riverlib/_info
techmap/*
!techmap/_info
ethlib/*
!ethlib/_info
misclib/*
!misclib/_info
work/*
!work/_info

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.