Subversion Repositories robust_axi_fabric

<##//////////////////////////////////////////////////////////////////
////                                                             ////
////  Author: Eyal Hochberg                                      ////
////          eyal@provartec.com                                 ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2010 Provartec LTD                            ////
//// www.provartec.com                                           ////
//// info@provartec.com                                          ////
////                                                             ////
//// This source file may be used and distributed without        ////
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//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
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//// This source file is free software; you can redistribute it  ////
//// and/or modify it under the terms of the GNU Lesser General  ////
//// Public License as published by the Free Software Foundation.////
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//// This source is distributed in the hope that it will be      ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
////                                                             ////
//////////////////////////////////////////////////////////////////##>

##Static defines
SWAP MODEL_NAME AXI interconnect fabric

SWAP MSTRS MASTER_NUM
SWAP SLVS EXPR(SLAVE_NUM+DVAL(DEF_DECERR_SLV))

LOOP MX MSTRS
LOOP SX SLVS

SWAP MSTR_BITS LOG2(MSTRS) 
SWAP SLV_BITS  LOG2(SLVS) 

SWAP SERR EXPR(SLVS-1)

GROUP IC_AXI_A is {
    ID       ID_BITS                input
    ADDR     ADDR_BITS              input
    LEN      4                      input
    SIZE     2                      input
    BURST    2                      input
    CACHE    4                      input
    PROT     3                      input
    LOCK     2                      input
    USER     USER_BITS              input
    VALID    1                      input
    READY    1                      output
}

GROUP IC_AXI_W is {
    ID        ID_BITS                input
    DATA      DATA_BITS              input
    STRB      DATA_BITS/8            input
    LAST      1                      input
    USER      USER_BITS              input
    VALID     1                      input
    READY     1                      output
}

GROUP IC_AXI_B is {
    ID        ID_BITS                output
    RESP      2                      output
    USER      USER_BITS              output
    VALID     1                      output
    READY     1                      input
}

GROUP IC_AXI_R is {
    ID        ID_BITS                output
    DATA      DATA_BITS              output
    RESP      2                      output
    LAST      1                      output
    USER      USER_BITS              output
    VALID     1                      output
    READY     1                      input
}

GROUP IC_AXI joins {
    GROUP IC_AXI_A prefix_AW
    GROUP IC_AXI_W prefix_W
    GROUP IC_AXI_B prefix_B
    GROUP IC_AXI_A prefix_AR
    GROUP IC_AXI_R prefix_R
}

GROUP IC_AXI_CMD is {
    SLV       SLV_BITS               input
    ID        ID_BITS                input
    VALID     1                      input
    READY     1                      input
}