URL
https://opencores.org/ocsvn/robust_reg/robust_reg/trunk
Subversion Repositories robust_reg
[/] [robust_reg/] [trunk/] [src/] [base/] [def_regfile.txt] - Rev 16
Compare with Previous | Blame | View Log
<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
REQUIRE(1.5)
STARTUSER
PARAM COUNT 0
INCLUDE def_regs.txt
SWAP.GLOBAL MODEL_NAME PREFIX configuration registers
SWAP FFD 1 ##flip-flop delay
## Types:
## RW - read / write (output from block)
## RO - read only (input to block)
## WO - write only (output to block)
## IW - internal write (output to block - logic is added especially)
## IR - internal read (no port - logic is added especially)
ENUM TYPE_RW TYPE_RO TYPE_WO TYPE_IW TYPE_IR
SWAP TYPE_TYPE_RW Read and Write
SWAP TYPE_TYPE_RO Read only
SWAP TYPE_TYPE_WO Write only
GROUP APB is {
pclken 1 input
psel 1 input
penable 1 input
paddr ADDR_BITS input
pwrite 1 input
pwdata 32 input
prdata 32 output
pslverr 1 output
pready 1 output
}
SWAP.USER ADD_REG(NAME, ADDR, TYPE, DESC) PARAM REG_NAME COUNT +NEWLINE PARAM COUNT +1 +NEWLINE GROUP.USER REGS extends { +NEWLINE NAME SON(CONST(ADDR) ADDR) SON(CONST(TYPE) TYPE) SON(CONST(DESC) DESC) +NEWLINE } ##Registers:
SWAP.USER ADD_FIELD(REGNAME, NAME, BITS, FIRST_BIT, DEFAULT, TYPE, DESC) GROUP.USER REGREG_REGNAME extends { +NEWLINE NAME BITS SON(CONST(FIRST_BIT) FIRST_BIT) SON(CONST(DEFAULT) DEFAULT) SON(CONST(TYPE) TYPE) SON(CONST(DESC) DESC) +NEWLINE } ##Fields: