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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_plp.v] - Rev 31
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// ============================================================================ // __ // \\__/ o\ (C) 2013 Robert Finch, Stratford // \ __ / All rights reserved. // \/_// robfinch<remove>@opencores.org // || // // This source file is free software: you can redistribute it and/or modify // it under the terms of the GNU Lesser General Public License as published // by the Free Software Foundation, either version 3 of the License, or // (at your option) any later version. // // This source file is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program. If not, see <http://www.gnu.org/licenses/>. // // ============================================================================ // BYTE_PLP1: if (unCachedData) begin cyc_o <= 1'b1; stb_o <= 1'b1; sel_o <= 4'hF; adr_o <= {radr,2'b00}; state <= BYTE_PLP2; end else if (dhit) begin cf <= rdat8[0]; zf <= rdat8[1]; im <= rdat8[2]; df <= rdat8[3]; bf <= rdat8[4]; vf <= rdat8[6]; nf <= rdat8[7]; state <= IFETCH; end else dmiss <= `TRUE; BYTE_PLP2: if (ack_i) begin cyc_o <= 1'b0; stb_o <= 1'b0; sel_o <= 4'h0; adr_o <= 34'd0; cf <= dati[0]; zf <= dati[1]; im <= dati[2]; df <= dati[3]; bf <= dati[4]; vf <= dati[6]; nf <= dati[7]; state <= IFETCH; end else if (err_i) begin lock_o <= 1'b0; cyc_o <= 1'b0; stb_o <= 1'b0; we_o <= 1'b0; sel_o <= 4'h0; adr_o <= 34'h0; dat_o <= 32'h0; state <= BUS_ERROR; end
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