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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [overflow.v] - Rev 33
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// ============================================================================ // __ // \\__/ o\ (C) 2013 Robert Finch, Stratford // \ __ / All rights reserved. // \/_// robfinch<remove>@opencores.org // || // // // This source file is free software: you can redistribute it and/or modify // it under the terms of the GNU Lesser General Public License as published // by the Free Software Foundation, either version 3 of the License, or // (at your option) any later version. // // This source file is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program. If not, see <http://www.gnu.org/licenses/>. // // ============================================================================ // module overflow(op, a, b, s, v); input op; // 0=add,1=sub input a; input b; input s; // sum output v; // Overflow: // Add: the signs of the inputs are the same, and the sign of the // sum is different // Sub: the signs of the inputs are different, and the sign of // the sum is the same as B assign v = (op ^ s ^ b) & (~op ^ a ^ b); endmodule
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