URL
https://opencores.org/ocsvn/rtf65002/rtf65002/trunk
Subversion Repositories rtf65002
[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [rts.v] - Rev 23
Go to most recent revision | Compare with Previous | Blame | View Log
// ============================================================================ // __ // \\__/ o\ (C) 2013 Robert Finch, Stratford // \ __ / All rights reserved. // \/_// robfinch<remove>@opencores.org // || // // This source file is free software: you can redistribute it and/or modify // it under the terms of the GNU Lesser General Public License as published // by the Free Software Foundation, either version 3 of the License, or // (at your option) any later version. // // This source file is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program. If not, see <http://www.gnu.org/licenses/>. // // ============================================================================ // RTS1: if (unCachedData) begin cyc_o <= 1'b1; stb_o <= 1'b1; sel_o <= 4'hF; adr_o <= {radr,2'b00}; state <= RTS2; end else if (dhit) begin isp <= isp_inc; pc <= rdat; state <= IFETCH; end else dmiss <= `TRUE; RTS2: if (ack_i) begin cyc_o <= 1'b0; stb_o <= 1'b0; sel_o <= 4'h0; adr_o <= 34'h0; isp <= isp_inc; pc <= dat_i; state <= IFETCH; end else if (err_i) begin lock_o <= 1'b0; cyc_o <= 1'b0; stb_o <= 1'b0; we_o <= 1'b0; sel_o <= 4'h0; adr_o <= 34'h0; dat_o <= 32'h0; state <= BUS_ERROR; end
Go to most recent revision | Compare with Previous | Blame | View Log