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[/] [rtftextcontroller/] [trunk/] [rtl/] [verilog/] [change_det.v] - Rev 21

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/* ===============================================================
	(C) 2006 Robert Finch
	All rights reserved.
	rob@birdcomputer.ca
 
	change_det.v
	- detects a change in a value
 
	This source code is free for use and modification for
	non-commercial or evaluation purposes, provided this
	copyright statement and disclaimer remains present in
	the file.
 
	If you do modify the code, please state the origin and
	note that you have modified the code.
 
	NO WARRANTY.
	THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF
	ANY KIND, WHETHER EXPRESS OR IMPLIED. The user must assume
	the entire risk of using the Work.
 
	IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
	ANY INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES
	WHATSOEVER RELATING TO THE USE OF THIS WORK, OR YOUR
	RELATIONSHIP WITH THE AUTHOR.
 
	IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU
	TO USE THE WORK IN APPLICATIONS OR SYSTEMS WHERE THE
	WORK'S FAILURE TO PERFORM CAN REASONABLY BE EXPECTED
	TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN LOSS
	OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK,
	AND YOU AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS
	FROM ANY CLAIMS OR LOSSES RELATING TO SUCH UNAUTHORIZED
	USE.
 
=============================================================== */
 
module change_det(rst, clk, ce, i, cd);
	parameter WID=32;
	input rst;			// reset
	input clk;			// clock
	input ce;			// clock enable
	input [WID:1] i;	// input signal
	output cd;			// change detected
 
	reg [WID:1] hold;
 
	always @(posedge clk)
		if (rst)
			hold <= i;
		else if (ce)
			hold <= i;
 
	assign cd = i != hold;
 
endmodule
 

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