Subversion Repositories rv01_riscv_core

#-----------------------------------------------------------------
#--                                                             --
#-----------------------------------------------------------------
#--                                                             --
#-- Copyright (C) 2017 Stefano Tonello                          --
#--                                                             --
#-- This source file may be used and distributed without        --
#-- restriction provided that this copyright statement is not   --
#-- removed from the file and that any derivative work contains --
#-- the original copyright notice and the associated disclaimer.--
#--                                                             --
#-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY         --
#-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   --
#-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   --
#-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      --
#-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         --
#-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    --
#-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   --
#-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        --
#-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  --
#-- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  --
#-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  --
#-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         --
#-- POSSIBILITY OF SUCH DAMAGE.                                 --
#--                                                             --
#-----------------------------------------------------------------

#---------------------------------------------------------------
# RV01 self-test module simulation script for Modelsim
# simulator.
#---------------------------------------------------------------

set SRC_DIR ../../VHDL

# -----------------------------------------
# Packages
# -----------------------------------------

vcom $SRC_DIR/RV01_consts_pkg.vhd
vcom $SRC_DIR/RV01_types_pkg.vhd
vcom $SRC_DIR/RV01_funcs_pkg.vhd
vcom $SRC_DIR/RV01_arith_pkg.vhd
vcom $SRC_DIR/RV01_op_pkg.vhd
vcom $SRC_DIR/RV01_csr_pkg.vhd
vcom $SRC_DIR/RV01_idec_pkg.vhd
vcom $SRC_DIR/RV01_div_funcs_pkg.vhd
vcom $SRC_DIR/RV01_plic_pkg.vhd

# -----------------------------------------
# Configuration package
# -----------------------------------------

vcom $SRC_DIR/SELF_TEST/RV01_cfg_dhrystone_sodor_st_pkg.vhd

# -----------------------------------------
# VHDL code
# -----------------------------------------

vcom $SRC_DIR/RV01_adder_f.vhd
vcom $SRC_DIR/RV01_ftchlog_1w.vhd
vcom $SRC_DIR/RV01_ftchlog_2w.vhd
vcom $SRC_DIR/RV01_idec.vhd
vcom $SRC_DIR/RV01_ifq.vhd
vcom $SRC_DIR/RV01_pstllog_2w_p6.vhd
vcom $SRC_DIR/RV01_isslog.vhd
vcom $SRC_DIR/RV01_mulu.vhd
vcom $SRC_DIR/RV01_shftu.vhd
vcom $SRC_DIR/RV01_logicu.vhd
vcom $SRC_DIR/RV01_pipe_a.vhd
vcom $SRC_DIR/RV01_pipe_b.vhd
vcom $SRC_DIR/RV01_lsu.vhd
vcom $SRC_DIR/RV01_sbuf_2w.vhd
vcom $SRC_DIR/RV01_regfile_32x32_2w.vhd
vcom $SRC_DIR/RV01_rams.vhd
vcom $SRC_DIR/RV01_bjxlog.vhd
vcom $SRC_DIR/RV01_bjxlog_bv.vhd
vcom $SRC_DIR/RV01_bht.vhd
vcom $SRC_DIR/RV01_bpu.vhd
vcom $SRC_DIR/RV01_pxlog.vhd
vcom $SRC_DIR/RV01_fwdlog_2w_p6.vhd
vcom $SRC_DIR/RV01_lzdu.vhd
vcom $SRC_DIR/RV01_divlog.vhd
vcom $SRC_DIR/RV01_divider_r2.vhd
vcom $SRC_DIR/RV01_csru.vhd
vcom $SRC_DIR/RV01_comp32.vhd
vcom $SRC_DIR/RV01_dimslog.vhd
vcom $SRC_DIR/RV01_excplog_ix1.vhd
vcom $SRC_DIR/RV01_excplog_ix2.vhd
vcom $SRC_DIR/RV01_excplog_ix3.vhd
vcom $SRC_DIR/RV01_dbglog_ix2.vhd
vcom $SRC_DIR/RV01_hltlog_ix2.vhd
# -----------------------------------------
# Debug module (not used by self-test module)
# -----------------------------------------
#vcom $SRC_DIR/RV01_dbgu.vhd
vcom $SRC_DIR/RV01_hltu.vhd
vcom $SRC_DIR/RV01_resmux_ix1.vhd
vcom $SRC_DIR/RV01_resmux_ix2.vhd
vcom $SRC_DIR/RV01_resmux_ix3.vhd
vcom $SRC_DIR/RV01_cdcomux.vhd
vcom $SRC_DIR/RV01_misclog_ix3.vhd
vcom $SRC_DIR/RV01_stack.vhd
vcom $SRC_DIR/RV01_queue.vhd
vcom $SRC_DIR/RV01_jrpu.vhd
# -----------------------------------------
# PLIC module (not used by self-test module)
# -----------------------------------------
#vcom $SRC_DIR/RV01_plic_gway.vhd
#vcom $SRC_DIR/RV01_plic_core.vhd
#vcom $SRC_DIR/RV01_plic.vhd
vcom $SRC_DIR/RV01_cpu_init.vhd
vcom $SRC_DIR/RV01_cpu_2w_p6.vhd
vcom $SRC_DIR/RV01_top.vhd
vcom $SRC_DIR/RV01_top_nohost.vhd
# -----------------------------------------
# Self-Test module & test-bench
# -----------------------------------------
vcom $SRC_DIR/SELF_TEST/dhrystone_sodor_st_rom.vhd
vcom $SRC_DIR/SELF_TEST/RV01_selftest.vhd
vcom $SRC_DIR/SELF_TEST/RV01_selftest_TB.vhd

vsim work.rv01_selftest_tb

# -----------------------------------------
# Waveforms
# -----------------------------------------
add wave /rv01_selftest_tb/clk
add wave /rv01_selftest_tb/rst
add wave /rv01_selftest_tb/done
add wave /rv01_selftest_tb/pass

run 1.1ms