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[/] [rv01_riscv_core/] [trunk/] [VHDL/] [RV01_cpu_init.vhd] - Rev 2
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----------------------------------------------------------------- -- -- ----------------------------------------------------------------- -- -- -- Copyright (C) 2015 Stefano Tonello -- -- -- -- This source file may be used and distributed without -- -- restriction provided that this copyright statement is not -- -- removed from the file and that any derivative work contains -- -- the original copyright notice and the associated disclaimer.-- -- -- -- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- -- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- -- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- -- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- -- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- -- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- -- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- -- POSSIBILITY OF SUCH DAMAGE. -- -- -- ----------------------------------------------------------------- --------------------------------------------------------------- -- RV01 CPU initialization control --------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.RV01_CONSTS_PKG.all; use work.RV01_TYPES_PKG.all; use work.RV01_FUNCS_PKG.all; use work.RV01_CSR_PKG.all; entity RV01_CPU_INIT is port( CLK_i : in std_logic; RST_i : in std_logic; STRT_i : in std_logic; RSM_i : in std_logic; BHT_INIT_END_i : in std_logic; INIT_STRT_o : out std_logic; STRT_o : out std_logic ); end RV01_CPU_INIT; architecture ARC of RV01_CPU_INIT is signal INIT_q : std_logic; signal INITD_q : std_logic; signal INIT_END : std_logic; begin ---------------------------------------------- -- This module insures that instruction -- execution starts only after BPU initialization -- is complete, to this purpose a start execution -- request coming on STRT_i can be delayed until -- BPU notifies initialization is over. -- When BPU is not present, this module is -- omitted from the core and start execution -- requests are always processed immediately. ---------------------------------------------- -- Initialization Done flag register, -- this register is cleared at reset -- and asserted when BPU initialization -- completes. process(CLK_i) begin if(CLK_i = '1' and CLK_i'event) then if(RST_i = '1') then INITD_q <= '0'; elsif(INIT_END = '1') then INITD_q <= '1'; end if; end if; end process; -- Initialization Done flag, asserted -- by BPU when it completes initialization. INIT_END <= BHT_INIT_END_i; -- Initialization start flag, BPU -- initialization is started whenever START_i -- is asserted, if initialization has not -- already been completed and there no -- pending start request. INIT_STRT_o <= STRT_i and not(INITD_q) and not(INIT_q); -- (Pending) start flag register, this -- register is needed because a start execution -- request coming during initialization must be -- held until initialization is complete. process(CLK_i) begin if(CLK_i = '1' and CLK_i'event) then if(RST_i = '1') then INIT_q <= '0'; elsif(STRT_i = '1' and INITD_q = '0') then INIT_q <= '1'; elsif(INIT_END = '1') then INIT_q <= '0'; end if; end if; end process; -- Start execution flag, this flag is asserted when -- 1) there's a pending start request when -- initialization complete, OR -- 2) there's a start request and initialization is -- already complete. STRT_o <= (INIT_q and INIT_END) or (STRT_i and INITD_q); end ARC;