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https://opencores.org/ocsvn/rv01_riscv_core/rv01_riscv_core/trunk
Subversion Repositories rv01_riscv_core
[/] [rv01_riscv_core/] [trunk/] [VHDL/] [RV01_csr_pkg.vhd] - Rev 2
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----------------------------------------------------------------- -- -- ----------------------------------------------------------------- -- -- -- Copyright (C) 2015 Stefano Tonello -- -- -- -- This source file may be used and distributed without -- -- restriction provided that this copyright statement is not -- -- removed from the file and that any derivative work contains -- -- the original copyright notice and the associated disclaimer.-- -- -- -- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- -- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- -- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- -- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- -- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- -- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- -- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- -- POSSIBILITY OF SUCH DAMAGE. -- -- -- ----------------------------------------------------------------- --------------------------------------------------------------- -- RV01 constants package --------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library WORK; use WORK.RV01_CONSTS_PKG.all; use WORK.RV01_TYPES_PKG.all; package RV01_CSR_PKG is -- CSR address width constant CSR_ADR_WIDTH : natural := 12; -- CSR address type subtype CSR_ADR_T is unsigned(CSR_ADR_WIDTH-1 downto 0); -- Debug port address width constant DBG_ADR_WIDTH : natural := 16; -- Debug port address type subtype DBG_ADR_T is unsigned(DBG_ADR_WIDTH-1 downto 0); -- User-level CSR addresses constant UFFLAGS_ADR : CSR_ADR_T := X"001"; constant UFRM_ADR : CSR_ADR_T := X"002"; constant UFCSR_ADR : CSR_ADR_T := X"003"; constant UCYCLE_ADR : CSR_ADR_T := X"C00"; constant UCYCLEH_ADR : CSR_ADR_T := X"C80"; constant UTIME_ADR : CSR_ADR_T := X"C01"; constant UTIMEH_ADR : CSR_ADR_T := X"C81"; constant UINSTRET_ADR : CSR_ADR_T := X"C02"; constant UINSTRETH_ADR : CSR_ADR_T := X"C82"; -- this CSR is added only for compatibility -- with sodor core. constant USTATS_ADR : CSR_ADR_T := X"0C0"; -- Machine-level CSR addresses constant MCPUID_ADR : CSR_ADR_T := X"F00"; constant MIMPID_ADR : CSR_ADR_T := X"F01"; constant MHARTID_ADR : CSR_ADR_T := X"F10"; constant MSTATUS_ADR : CSR_ADR_T := X"300"; constant MTVEC_ADR : CSR_ADR_T := X"301"; constant MTDELEG_ADR : CSR_ADR_T := X"302"; constant MIE_ADR : CSR_ADR_T := X"304"; constant MTIMECMP_ADR : CSR_ADR_T := X"321"; constant MTIME_ADR : CSR_ADR_T := X"701"; constant MTIMEH_ADR : CSR_ADR_T := X"741"; constant MSCRATCH_ADR : CSR_ADR_T := X"340"; constant MEPC_ADR : CSR_ADR_T := X"341"; constant MCAUSE_ADR : CSR_ADR_T := X"342"; constant MBADADDR_ADR : CSR_ADR_T := X"343"; constant MIP_ADR : CSR_ADR_T := X"344"; constant MBASE_ADR : CSR_ADR_T := X"380"; constant MBOUND_ADR : CSR_ADR_T := X"381"; constant MIBASE_ADR : CSR_ADR_T := X"382"; constant MIBOUND_ADR : CSR_ADR_T := X"383"; constant MDBASE_ADR : CSR_ADR_T := X"384"; constant MDBOUND_ADR : CSR_ADR_T := X"385"; constant HTIMEW_ADR : CSR_ADR_T := X"B01"; constant HTIMEHW_ADR : CSR_ADR_T := X"B81"; -- Non standard Machine-level CSR addresses -- Host interface constant MTOHOST_ADR : CSR_ADR_T := X"780"; constant MFROMHOST_ADR : CSR_ADR_T := X"781"; -- RV01 core control constant MRV01CC_ADR : CSR_ADR_T := X"782"; -- RV01 halt control constant MRV01HC_ADR : CSR_ADR_T := X"784"; -- RV01 halt address constant MRV01HA_ADR : CSR_ADR_T := X"785"; -- RV01 halt address constant MRV01RA_ADR : CSR_ADR_T := X"786"; -- Debug Module CSR addresses --constant DCCS_ADR : CSR_ADR_T := X"770"; --constant DDTMMA_ADR : CSR_ADR_T := X"771"; --constant DDCS_ADR : CSR_ADR_T := X"772"; --constant DDPC_ADR : CSR_ADR_T := X"773"; --constant DDMBX0_ADR : CSR_ADR_T := X"774"; --constant DDMBX1_ADR : CSR_ADR_T := X"775"; --constant DDS_ADR : CSR_ADR_T := X"776"; --constant DPCS_ADR : CSR_ADR_T := X"777"; constant CCS_ADR : DBG_ADR_T := X"0000"; constant DTMIA_ADR : DBG_ADR_T := X"0010"; constant DCS_ADR : DBG_ADR_T := X"0020"; constant PCS_ADR : DBG_ADR_T := X"0030"; constant SI_ADR : DBG_ADR_T := X"0100"; constant DJ_ADR : DBG_ADR_T := X"0110"; constant PC_ADR : DBG_ADR_T := X"0120"; -- CSR write masks constant UFCSR_WMSK : SDWORD_T := X"000000ff"; constant UFFLAGS_WMSK : SDWORD_T := X"0000001f"; constant UFRM_WMSK : SDWORD_T := X"00000007"; constant MSTATUS_WMSK : SDWORD_T := X"001f0fff"; constant MTVEC_WMSK : SDWORD_T := X"fffffffc"; constant MIE_WMSK : SDWORD_T := X"00000088"; constant MEPC_WMSK : SDWORD_T := X"fffffffc"; constant MCAUSE_WMSK : SDWORD_T := X"8000000f"; constant MIP_WMSK : SDWORD_T := X"00000008"; constant MRV01CC_WMSK : SDWORD_T := X"00000001"; constant MRV01HC_WMSK : SDWORD_T := X"00000030"; constant CCS_WMSK : SDWORD_T := X"0f0200ff"; constant DCS_WMSK : SDWORD_T := X"0000000f"; -- CSR's read-only content -- mcpuid is read-only (value: RV32I with "M" extension) constant MCPUID_RO : SDWORD_T := X"00001000"; -- mimpid is read-only (value: anonymous source) constant MIMPID_RO : SDWORD_T := X"00008000"; -- mihartid is read-only (value: all-0) constant MHARTID_RO : SDWORD_T := X"00000000"; -- mtdeleg is read-only (value: all-0) constant MTDELEG_RO : SDWORD_T := X"00000000"; -- CSR's reset content -- mstatus ( -- SD = 0, -- VM = 0, -- MPRV = 0, -- FS = 0, -- XS = 0, -- PRV1/3 = 00, -- IE1/3 = 1 -- PRV = 11, -- IE = 0 --) constant MSTATUS_RST : SDWORD_T := X"0000024e"; -- mtvec (low trap vector location) constant MTVEC_RST : SDWORD_T := X"00000100"; -- mie (no enabled timer interrupts) constant MIE_RST : SDWORD_T := X"00000000"; -- mip (no pending timer interrupts) constant MIP_RST : SDWORD_T := X"00000000"; -- mrv01cc ( -- pxe=1 --) constant MRV01CC_RST : SDWORD_T := X"00000001"; -- mrv01hc ( -- haltstate=1 --) constant MRV01HC_RST : SDWORD_T := X"00000001"; -- CCS ( -- 31 - authenticated = 1 -- 30 - authbusy = 0 -- 27 - ndreset = 0 -- 26 - fullreset = 0 -- 25 - stopcycle = 1 -- 24 - stoptime = 1 -- 23 - frozen = 0 -- 22 - freezesup = 0 -- 21 - freezeresume = 0 -- 20 - freezeresume = 0 -- 19 - halted = 1 -- 18 - haltsup = 1 -- 17 - halt = 0 -- 16 - resume = 0 -- 7:0 - interrupt = 0x0000 --) constant CCS_RST : SDWORD_T := X"830c0000"; -- DCS ( -- 31 - pcsample = 1 -- 30 - haltinterrupt = 0 -- 29:28 - xdebugver = 01 -- 27:16 - hwbpcount = 0x000 -- 7 - debug = 1 -- 6:4 - cause = 011 -- 3 - ebreakm = 0 -- 2 - ebreakh = 0 -- 1 - ebreaks = 0 -- 0 - ebreaku = 0 --) constant DCS_RST : SDWORD_T := X"900000b0"; -- mcause patterns constant IADRMIS : std_logic_vector(5-1 downto 0) := "00000"; constant IACCFLT : std_logic_vector(5-1 downto 0) := "00001"; constant ILLGINS : std_logic_vector(5-1 downto 0) := "00010"; constant BRKPNT : std_logic_vector(5-1 downto 0) := "00011"; constant LADRMIS : std_logic_vector(5-1 downto 0) := "00100"; constant LACCFLT : std_logic_vector(5-1 downto 0) := "00101"; constant SADRMIS : std_logic_vector(5-1 downto 0) := "00110"; constant SACCFLT : std_logic_vector(5-1 downto 0) := "00111"; constant UMCALL : std_logic_vector(5-1 downto 0) := "01000"; constant SMCALL : std_logic_vector(5-1 downto 0) := "01001"; constant HMCALL : std_logic_vector(5-1 downto 0) := "01010"; constant MMCALL : std_logic_vector(5-1 downto 0) := "01011"; constant SOFTINT : std_logic_vector(5-1 downto 0) := "10000"; constant TIMRINT : std_logic_vector(5-1 downto 0) := "10001"; constant EXTINT : std_logic_vector(5-1 downto 0) := "10010"; -- address enviroments constant MBARE : std_logic_vector(4-1 downto 0) := "0000"; constant MBB : std_logic_vector(4-1 downto 0) := "0001"; constant MBBID : std_logic_vector(4-1 downto 0) := "0010"; -- mtvec allowed values constant MTVEC_LO : unsigned(SDLEN-1 downto 0) := X"00000100"; constant MTVEC_HI : unsigned(SDLEN-1 downto 0) := X"fffffe00"; -- trap/interrupt vector address (low address version) constant UTRAP_VA_LO : unsigned(SDLEN-1 downto 0) := X"00000100"; constant STRAP_VA_LO : unsigned(SDLEN-1 downto 0) := X"00000140"; constant HTRAP_VA_LO : unsigned(SDLEN-1 downto 0) := X"00000180"; constant MTRAP_VA_LO : unsigned(SDLEN-1 downto 0) := X"000001C0"; constant NMINT_VA_LO : unsigned(SDLEN-1 downto 0) := X"000001FC"; constant RESET_VA_LO : unsigned(SDLEN-1 downto 0) := X"00000200"; -- trap/interrupt vector address (high address version) constant UTRAP_VA_HI : unsigned(SDLEN-1 downto 0) := X"fffffe00"; constant STRAP_VA_HI : unsigned(SDLEN-1 downto 0) := X"fffffe40"; constant HTRAP_VA_HI : unsigned(SDLEN-1 downto 0) := X"fffffe80"; constant MTRAP_VA_HI : unsigned(SDLEN-1 downto 0) := X"fffffeC0"; constant NMINT_VA_HI : unsigned(SDLEN-1 downto 0) := X"fffffeFC"; constant RESET_VA_HI : unsigned(SDLEN-1 downto 0) := X"ffffff00"; end package; package body RV01_CSR_PKG is end package body;