Subversion Repositories rv01_riscv_core

-----------------------------------------------------------------
--                                                             --
-----------------------------------------------------------------
--                                                             --
-- Copyright (C) 2015 Stefano Tonello                          --
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-----------------------------------------------------------------
 
---------------------------------------------------------------
-- RV01 halt logic (IX2 stage)
---------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all; 
use IEEE.numeric_std.all;
 
library work;
use work.RV01_CONSTS_PKG.all;
use work.RV01_TYPES_PKG.all;
use work.RV01_IDEC_PKG.all;
 
entity RV01_HLTLOG_IX2 is
  generic(
    NW : natural := 2
  );
  port(
    V_i : in std_logic_vector(NW-1 downto 0);
    IMNMC0_i : in INST_MNEMONIC_T;
    PC0_i : in unsigned(ALEN-1 downto 0);
    PC1_i : in unsigned(ALEN-1 downto 0);
    HOBRK_i : in std_logic;
    HOADR_i : in std_logic_vector(NW-1 downto 0);
    HADR_i : in unsigned(ALEN-1 downto 0);
    HRQ_i : in std_logic;
 
    HALT_o : out std_logic_vector(NW-1 downto 0);
    HIS_o : out std_logic
  );
end RV01_HLTLOG_IX2;
 
architecture ARC of RV01_HLTLOG_IX2 is
 
  signal BRK0,HOBRK0 : std_logic;
  signal HOADR : std_logic_vector(NW-1 downto 0);
 
begin
 
  -- Halt via HLT_i/HOBRK_i/HOADR_i/HADR_i interface.
 
  -- Instruction execution is halted on the first valid
  -- instruction which:
  -- 1) is a sbreak (if HOBRK_i = '1'), OR
  -- 2) fetch address matches HADR_i (if HOADR_i = '1'), OR
  -- 3) reaches IX3 when HRQ_i = '1'.
 
  -- Halting may occurs with some delay with respect to HLT_i
  -- assertion because it's "triggered" by a valid instruction.
 
  -- Instruction execution restarts when RSM_q and STRT_q are both '1'.
  -- Restarting is immediate.
 
  -- sbreak instruction flag
  BRK0 <= '1' when (IMNMC0_i = IM_SBREAK) else '0';
 
  -- halt-on-break flag
  HOBRK0 <= HOBRK_i and BRK0;
 
  -- halt-on-address flags
  HOADR(0) <= HOADR_i(0) when (PC0_i = HADR_i) else '0';
  HOADR(1) <= HOADR_i(1) when (PC1_i = HADR_i) else '0';
 
  -- final halt flags
  HALT_o(0) <= V_i(0) and (HOBRK0 or HOADR(0) or HRQ_i);
  HALT_o(1) <= V_i(1) and (HOADR(1) or HRQ_i);
 
  -- halt instruction selector
  HIS_o <= '0' when (
    HOBRK0 = '1' or
    HOADR(0) = '1' or 
    (V_i(0) = '1' and HRQ_i = '1')
  ) else '1';
 
end ARC;