Subversion Repositories rv01_riscv_core

-----------------------------------------------------------------
--                                                             --
-----------------------------------------------------------------
--                                                             --
-- Copyright (C) 2015 Stefano Tonello                          --
--                                                             --
-- This source file may be used and distributed without        --
-- restriction provided that this copyright statement is not   --
-- removed from the file and that any derivative work contains --
-- the original copyright notice and the associated disclaimer.--
--                                                             --
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY         --
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   --
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   --
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      --
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         --
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    --
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   --
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        --
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  --
-- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  --
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  --
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         --
-- POSSIBILITY OF SUCH DAMAGE.                                 --
--                                                             --
-----------------------------------------------------------------
 
---------------------------------------------------------------
-- Instruction decoding data types
---------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
library work;
use work.RV01_CONSTS_PKG.all;
use work.RV01_TYPES_PKG.all;
use work.RV01_OP_PKG.all;
use work.RV01_CSR_PKG.all;
 
package RV01_IDEC_PKG is
 
  type INST_MNEMONIC_T is (
    IM_ADDI,
    IM_SLTI,
    IM_SLTIU,
    IM_ANDI,
    IM_ORI,
    IM_XORI,
    IM_SLLI,
    IM_SRAI,
    IM_SRLI,
    IM_LUI,
    IM_AUIPC,
    IM_ADD,
    IM_SUB,
    IM_SLT,
    IM_SLTU,
    IM_AND,
    IM_OR,
    IM_XOR,
    IM_SLL,
    IM_SRA,
    IM_SRL,
    IM_J,
    IM_JAL,
    IM_JALR,
    IM_BEQ,
    IM_BNE,
    IM_BLT,
    IM_BLTU,
    IM_BGE,
    IM_BGEU,
    IM_LB,
    IM_LH,
    IM_LW,
    IM_LBU,
    IM_LHU,
    IM_SB,
    IM_SH,
    IM_SW,
    IM_FENCE,
    IM_FENCEI,
    IM_SCALL,
    IM_SBREAK,
    IM_ERET,
    IM_WFI,
    IM_SFENCEVM,
    IM_CSRRW,
    IM_CSRRS,
    IM_CSRRC,
    IM_CSRRWI,
    IM_CSRRSI,
    IM_CSRRCI,
    --IM_RDCYCLE,
    --IM_RDTIME,
    --IM_RDINSTRET,
    --IM_RDCYCLEH,
    --IM_RDTIMEH,
    --IM_RDINSTRETH,
 
    -- RV32M
 
    IM_MUL,
    IM_MULH,
    IM_MULHU,
    IM_MULHSU,
    IM_DIV,
    IM_DIVU,
    IM_REM,
    IM_REMU,
 
    -- RV32F
 
    IM_FLW,
    IM_FSW,
    IM_FADDS,
    IM_FSUBS,
    IM_FMULS,
    IM_FDIVS,
    -- IM_FMIN, -- not implemented
    -- IM_FMAX, -- not implemented
    -- IM_FSQRT, -- not implemented
    -- IM_FMADD, -- not implemented
    -- IM_FMSUB, -- not implemented
    -- IM_FNMADD, -- not implemented
    -- IM_FNMSUB, -- not implemented
    -- IM_FSGNJS, -- not implemented
    -- IM_FSGNJNS, -- not implemented
    -- IM_FSGNJXS, -- not implemented
    IM_FCVTWS,
    IM_FCVTSW,
    IM_FMVXS,
    IM_FMVSX,
    IM_FCMP,
    -- IM_FCLASS, -- not implemented
 
    IM_BAD_INSTR -- this is not a valid instruction!
  );
 
  type RES_SRC_T is (
    RS_PIPEA,
    RS_PIPEB,
    RS_LSU,
    RS_SIU,
    RS_DIVU,
    RS_NIL
  );
 
  type DEC_INSTR_T is record
    IMNMC : INST_MNEMONIC_T;
    WCSR : std_logic;
    WRD : std_logic;
    RRS1 : std_logic;
    RRS2 : std_logic;
    RD : RID_T;
    RS1 : RID_T;
    RS2 : RID_T;
    IMM : signed(SDLEN-1 downto 0);
    SU : std_logic;
    ALU_OP : ALU_OP_T;
    BJ_OP : BJ_OP_T;
    LS_OP : LS_OP_T;
    CS_OP : CS_OP_T;
    RES_SRC : RES_SRC_T;
    P0_ONLY : std_logic;
    P1_ONLY : std_logic;
    EXCP : std_logic;
    ECAUSE : std_logic_vector(5-1 downto 0);
    RFTCH : std_logic;
    SEQX : std_logic;
  end record;
 
  constant DEC_NIL : DEC_INSTR_T := (
    IM_BAD_INSTR,
    '0',
    '0',
    '0',
    '0',
    0,
    0,
    0,
    (others => '0'),
    '0',
    ALU_NIL,
    BJ_NIL,
    LS_NIL,
    CS_NIL,
    RS_NIL,
    '0',
    '0',
    '0',
    (others => '0'),
    '0',
    '0'
  );
 
  type DEC_INSTR_VEC_T is array (natural range<>) of DEC_INSTR_T;
 
  -- main opcode values
  constant OP_LUI     : std_logic_vector(7-1 downto 0) := "0110111"; --X"37";
  constant OP_AUIPC   : std_logic_vector(7-1 downto 0) := "0010111"; --X"17";
  constant OP_JAL     : std_logic_vector(7-1 downto 0) := "1101111"; --X"6f";
  constant OP_JALR    : std_logic_vector(7-1 downto 0) := "1100111"; --X"67";
  constant OP_BRANCH  : std_logic_vector(7-1 downto 0) := "1100011"; --X"63";
  constant OP_LOAD    : std_logic_vector(7-1 downto 0) := "0000011"; --X"03";
  constant OP_STORE   : std_logic_vector(7-1 downto 0) := "0100011"; --X"23";
  constant OP_ALUI    : std_logic_vector(7-1 downto 0) := "0010011"; --X"13";
  constant OP_ALU     : std_logic_vector(7-1 downto 0) := "0110011"; --X"33";
  constant OP_MISCMEM : std_logic_vector(7-1 downto 0) := "0001111"; --X"0f";
  constant OP_SYSTEM  : std_logic_vector(7-1 downto 0) := "1110011"; --X"73";
  -- "F" extension
  constant OP_LOADFP  : std_logic_vector(7-1 downto 0) := "0000111"; --X"07";
  constant OP_STOREFP : std_logic_vector(7-1 downto 0) := "0100111"; --X"27";
  constant OP_FP      : std_logic_vector(7-1 downto 0) := "1010011"; --X"53";
 
end package;