Subversion Repositories rv01_riscv_core

-----------------------------------------------------------------
--                                                             --
-----------------------------------------------------------------
--                                                             --
-- Copyright (C) 2015 Stefano Tonello                          --
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---------------------------------------------------------------
-- RV01 logic (boolean) unit
---------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all; 
use IEEE.numeric_std.all;
 
library WORK;
use WORK.RV01_CONSTS_PKG.all;
use WORK.RV01_TYPES_PKG.all;
use WORK.RV01_ARITH_PKG.all;
 
entity RV01_LOGICU is
  port(
    CTRL_i : in LOG_CTRL;
    OPA_i : in SDWORD_T;
    OPB_i : in SDWORD_T;
 
    RES_o : out SDWORD_T
  );
end RV01_LOGICU;
 
architecture ARC of RV01_LOGICU is
 
begin
 
  process(CTRL_i,OPA_i,OPB_i)
  begin
    case CTRL_i is
      when LC_AND =>
        RES_o(SDLEN-1 downto 0) <= (OPA_i and OPB_i); 
      when LC_OR =>
        RES_o(SDLEN-1 downto 0) <= (OPA_i or OPB_i); 
      when others => --LC_XOR
        RES_o(SDLEN-1 downto 0) <= (OPA_i xor OPB_i); 
    end case;
  end process;
 
end ARC;