Subversion Repositories rv01_riscv_core

-----------------------------------------------------------------
--                                                             --
-----------------------------------------------------------------
--                                                             --
-- Copyright (C) 2015 Stefano Tonello                          --
--                                                             --
-- This source file may be used and distributed without        --
-- restriction provided that this copyright statement is not   --
-- removed from the file and that any derivative work contains --
-- the original copyright notice and the associated disclaimer.--
--                                                             --
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY         --
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   --
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   --
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      --
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         --
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    --
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   --
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        --
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  --
-- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  --
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  --
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         --
-- POSSIBILITY OF SUCH DAMAGE.                                 --
--                                                             --
-----------------------------------------------------------------
 
---------------------------------------------------------------
-- 32-bit leading 0's detector
---------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
library WORK;
--use work.RV01_CONSTS_PKG.all;
--use work.RV01_TYPES_PKG.all;
use WORK.RV01_FUNCS_PKG.all;
--use WORK.RV01_ARITH_PKG.all;
 
entity RV01_LZD32 is
  generic(
    WIDTH : natural := 32
  );
  port(
    A_i : in std_logic_vector(WIDTH-1 downto 0);
 
    CNT_o : out std_logic_vector(6-1 downto 0)
  );
end RV01_LZD32;
 
architecture ARC of RV01_LZD32 is
 
  constant MAXZ : natural := 32;
  constant ONE : unsigned(WIDTH-1 downto 0) := to_unsigned(1,WIDTH);
 
  function CHK(
    U : unsigned(WIDTH-1 downto 0);
    N : natural range 0 to WIDTH-1
  ) return std_logic is
  begin
    if((U srl N) = ONE) then
      return('1');
    else
      return('0');
    end if;
  end function;
 
  signal CNT : natural range 0 to WIDTH;
 
begin
 
  process(A_i)
    variable TMP : std_logic_vector(MAXZ-1 downto 0);
  begin
    for i in 0 to MAXZ-1 loop
      TMP(i) := CHK(to_unsigned(A_i),i); 
    end loop;
    case TMP is
      when "10000000000000000000000000000000"=> CNT <= 0;
      when "01000000000000000000000000000000"=> CNT <= 1;
      when "00100000000000000000000000000000"=> CNT <= 2;
      when "00010000000000000000000000000000"=> CNT <= 3;
      when "00001000000000000000000000000000"=> CNT <= 4;
      when "00000100000000000000000000000000"=> CNT <= 5;
      when "00000010000000000000000000000000"=> CNT <= 6;
      when "00000001000000000000000000000000"=> CNT <= 7;
      when "00000000100000000000000000000000"=> CNT <= 8;
      when "00000000010000000000000000000000"=> CNT <= 9;
      when "00000000001000000000000000000000"=> CNT <= 10;
      when "00000000000100000000000000000000"=> CNT <= 11;
      when "00000000000010000000000000000000"=> CNT <= 12;
      when "00000000000001000000000000000000"=> CNT <= 13;
      when "00000000000000100000000000000000"=> CNT <= 14;
      when "00000000000000010000000000000000"=> CNT <= 15;
      when "00000000000000001000000000000000"=> CNT <= 16;
      when "00000000000000000100000000000000"=> CNT <= 17;
      when "00000000000000000010000000000000"=> CNT <= 18;
      when "00000000000000000001000000000000"=> CNT <= 19;
      when "00000000000000000000100000000000"=> CNT <= 20;
      when "00000000000000000000010000000000"=> CNT <= 21;
      when "00000000000000000000001000000000"=> CNT <= 22;
      when "00000000000000000000000100000000"=> CNT <= 23;
      when "00000000000000000000000010000000"=> CNT <= 24;
      when "00000000000000000000000001000000"=> CNT <= 25;
      when "00000000000000000000000000100000"=> CNT <= 26;
      when "00000000000000000000000000010000"=> CNT <= 27;
      when "00000000000000000000000000001000"=> CNT <= 28;
      when "00000000000000000000000000000100"=> CNT <= 29;
      when "00000000000000000000000000000010"=> CNT <= 30;
      when "00000000000000000000000000000001"=> CNT <= 31;
      when others => CNT <= 32;
    end case;
  end process;
 
  CNT_o <= to_std_logic_vector(to_unsigned(CNT,6));
 
end ARC;