Subversion Repositories rv01_riscv_core

-----------------------------------------------------------------
--                                                             --
-----------------------------------------------------------------
--                                                             --
-- Copyright (C) 2015 Stefano Tonello                          --
--                                                             --
-- This source file may be used and distributed without        --
-- restriction provided that this copyright statement is not   --
-- removed from the file and that any derivative work contains --
-- the original copyright notice and the associated disclaimer.--
--                                                             --
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY         --
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   --
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   --
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      --
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         --
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   --
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        --
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  --
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         --
-- POSSIBILITY OF SUCH DAMAGE.                                 --
--                                                             --
-----------------------------------------------------------------
 
---------------------------------------------------------------
-- RV01 pipeline-A (dedicated) decoder 
---------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all; 
use IEEE.numeric_std.all;
 
library WORK;
use WORK.RV01_CONSTS_PKG.all;
use WORK.RV01_TYPES_PKG.all;
use work.RV01_IDEC_PKG.all;
use WORK.RV01_OP_PKG.all;
 
entity RV01_PIPE_A_DEC is
  port(
    INSTR_i : in DEC_INSTR_T;
 
    FWDE_o : out std_logic;
    SEL_o :  out std_logic_vector(4-1 downto 0)
  );
end RV01_PIPE_A_DEC;
 
architecture ARC of RV01_PIPE_A_DEC is
 
begin
 
  -- Result forward-enable flag
 
  FWDE_o <= '1' when (
    INSTR_i.IMNMC = IM_ADD or
    INSTR_i.IMNMC = IM_ADDI or
    INSTR_i.IMNMC = IM_SLL or
    INSTR_i.IMNMC = IM_SLLI or
    INSTR_i.IMNMC = IM_SRL or
    INSTR_i.IMNMC = IM_SRLI or
    INSTR_i.IMNMC = IM_SRA or
    INSTR_i.IMNMC = IM_SRAI or
    INSTR_i.IMNMC = IM_AND or
    INSTR_i.IMNMC = IM_ANDI or
    INSTR_i.IMNMC = IM_OR or
    INSTR_i.IMNMC = IM_ORI or
    INSTR_i.IMNMC = IM_XOR or
    INSTR_i.IMNMC = IM_XORI or
    INSTR_i.IMNMC = IM_LW
  ) else '0';
 
  -- pipe-A operation selector
 
  process(INSTR_i)
  begin
    case INSTR_i.IMNMC is
      when IM_ADD|IM_ADDI => SEL_o <= "0001";
      when IM_SLL|IM_SLLI|IM_SRL|IM_SRLI|IM_SRA|IM_SRAI => SEL_o <= "0010";
      when IM_AND|IM_ANDI|IM_OR|IM_ORI|IM_XOR|IM_XORI  => SEL_o <= "0100";
      when others => SEL_o <= "1000"; -- lw
    end case;
  end process;
 
end ARC;
 
---------------------------------------------------------------
-- A-pipeline ALU
---------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all; 
use IEEE.numeric_std.all;
 
library WORK;
use WORK.RV01_CONSTS_PKG.all;
use WORK.RV01_TYPES_PKG.all;
use WORK.RV01_FUNCS_PKG.all;
use WORK.RV01_ARITH_PKG.all;
use work.RV01_IDEC_PKG.all;
use WORK.RV01_OP_PKG.all;
 
entity RV01_PIPE_A_ALU is
  port(
    SEL_i :  in std_logic_vector(4-1 downto 0);
    SU_i : in std_logic;
    OP_i : in ALU_OP_T;
    OPA_i : in SDWORD_T;
    OPB_i : in SDWORD_T;
 
    RES_o : out SDWORD_T --  result
  );
end RV01_PIPE_A_ALU;
 
architecture ARC of RV01_PIPE_A_ALU is
 
  constant OP_ADD : natural := 0;
  constant OP_SHF : natural := 1;
  constant OP_LOG : natural := 2;
  constant OP_LOAD : natural := 3;
 
  component RV01_ADDER_F is
    generic(
      LEN1 : integer := 16;
      LEN2 : integer := 16
    );
    port(
      OPA_i : in signed(LEN1+LEN2-1 downto 0);
      OPB_i : in signed(LEN1+LEN2-1 downto 0);
      CI_i : in std_logic;
 
      SUM_o : out signed(LEN1+LEN2-1 downto 0)
    );
  end component;
 
  component RV01_LOGICU is
    port(
      CTRL_i : in LOG_CTRL;
      OPA_i : in SDWORD_T;
      OPB_i : in SDWORD_T;
 
      RES_o : out SDWORD_T
    );
  end component;
 
  signal ZERO : std_logic := '0';
  signal ONE : std_logic := '1';
  signal ADD_RES : SDWORD_T;
  signal LOG_RES : SDWORD_T;
  signal LC : LOG_CTRL;
  signal RES : SDWORD_T;
 
begin
 
  ------------------------------------
  -- addition
  ------------------------------------
 
  -- carry-select adder (to improve timing)
 
  U_ADD : RV01_ADDER_F
    generic map(
      LEN1 => SDLEN/2,
      LEN2 => SDLEN/2
    )
    port map(
      OPA_i => OPA_i,
      OPB_i => OPB_i,
      CI_i => ZERO,
      SUM_o => ADD_RES
    );
 
  ------------------------------------
  -- Logic unit operation selection
  ------------------------------------
 
  process(OP_i)
  begin
    case OP_i is
      when ALU_AND =>
        LC <= LC_AND;
      when ALU_OR =>
        LC <= LC_OR;
      when others =>
        LC <= LC_XOR;
    end case;
  end process;
 
  ------------------------------------
  -- Logic unit
  ------------------------------------
 
  U_LOG : RV01_LOGICU
    port map(
      CTRL_i => LC,
      OPA_i => OPA_i,
      OPB_i => OPB_i,
 
      RES_o => LOG_RES
    );
 
  -- Result mux
 
  RES <= ADD_RES when (SEL_i(OP_ADD) = '1') else LOG_RES;
 
  RES_o <= RES;
 
end ARC;