Subversion Repositories rv01_riscv_core

-----------------------------------------------------------------
--                                                             --
-----------------------------------------------------------------
--                                                             --
-- Copyright (C) 2016 Stefano Tonello                          --
--                                                             --
-- This source file may be used and distributed without        --
-- restriction provided that this copyright statement is not   --
-- removed from the file and that any derivative work contains --
-- the original copyright notice and the associated disclaimer.--
--                                                             --
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY         --
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   --
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   --
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      --
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         --
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   --
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  --
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         --
-- POSSIBILITY OF SUCH DAMAGE.                                 --
--                                                             --
-----------------------------------------------------------------
 
---------------------------------------------------------------
-- RV01 PLIC
---------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all; 
use IEEE.numeric_std.all;
 
library work;
use work.RV01_CONSTS_PKG.all;
use work.RV01_FUNCS_PKG.all;
use work.RV01_PLIC_PKG.all;
 
entity RV01_PLIC is
  generic(
    SRC_CNT : natural := 8;
    TRIG_TYPE : PLIC_TRIG_TYPE := LEVEL;
    REQ_MAXCNT : natural := 16
  );
  port(
    CLK_i : in std_logic;
    RST_i : in std_logic;
    REG_A_i : in std_logic_vector(log2(SRC_CNT+1)-1 downto 0);
    REG_WE_i : in std_logic;
    REG_D_i : in std_logic_vector(SDLEN-1 downto 0);
    REQ_i : in std_logic_vector(SRC_CNT-1 downto 0);
 
    REG_Q_o : out std_logic_vector(SDLEN-1 downto 0);
    EIP_o : out std_logic
  );
end RV01_PLIC;
 
architecture ARC of RV01_PLIC is
 
  component RV01_PLIC_GWAY is
    generic(
      TRIG_TYPE : PLIC_TRIG_TYPE := LEVEL;
      REQ_MAXCNT : natural := 16
    );
    port(
      CLK_i : in std_logic;
      RST_i : in std_logic;
      REQ_i : in std_logic;
      IS_i : in std_logic;
 
      IP_o : out std_logic
    );
  end component ;
 
  component RV01_PLIC_CORE is
    generic(
      SRC_CNT : natural := 8
    );
    port(
      CLK_i : in std_logic;
      RST_i : in std_logic;
      REG_A_i : in std_logic_vector(log2(SRC_CNT+1)-1 downto 0);
      REG_WE_i : in std_logic;
      REG_D_i : in std_logic_vector(SDLEN-1 downto 0);
      IP_i : in std_logic_vector(SRC_CNT-1 downto 0);
 
      REG_Q_o : out std_logic_vector(SDLEN-1 downto 0);
      EIP_o : out std_logic;
      IS_o : out std_logic_vector(SRC_CNT-1 downto 0)
    );
  end component ;
 
  signal ISX : std_logic_vector(SRC_CNT-1 downto 0);
  signal IP : std_logic_vector(SRC_CNT-1 downto 0);
 
begin
 
  U_CORE : RV01_PLIC_CORE
    generic map(
      SRC_CNT => SRC_CNT
    )
    port map(
      CLK_i => CLK_i,
      RST_i => RST_i,
      REG_A_i => REG_A_i,
      REG_WE_i => REG_WE_i,
      REG_D_i => REG_D_i,
      IP_i => IP,
 
      REG_Q_o => REG_Q_o,
      EIP_o => EIP_o,
      IS_o => ISX
    );
 
  G0 : for k in 0 to SRC_CNT-1 generate
 
  U_GWAY : RV01_PLIC_GWAY
    generic map(
      TRIG_TYPE => TRIG_TYPE,
      REQ_MAXCNT => REQ_MAXCNT 
    )
    port map(
      CLK_i => CLK_i,
      RST_i => RST_i,
      REQ_i => REQ_i(k),
      IS_i => ISX(k),
 
      IP_o => IP(k)
    );
 
  end generate;
 
end ARC;