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[/] [rv01_riscv_core/] [trunk/] [VHDL/] [RV01_plic_gway.vhd] - Rev 2

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-----------------------------------------------------------------
--                                                             --
-----------------------------------------------------------------
--                                                             --
-- Copyright (C) 2016 Stefano Tonello                          --
--                                                             --
-- This source file may be used and distributed without        --
-- restriction provided that this copyright statement is not   --
-- removed from the file and that any derivative work contains --
-- the original copyright notice and the associated disclaimer.--
--                                                             --
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY         --
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   --
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   --
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      --
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         --
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    --
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   --
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        --
-- BUSINESS REQERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  --
-- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  --
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  --
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         --
-- POSSIBILITY OF SUCH DAMAGE.                                 --
--                                                             --
-----------------------------------------------------------------
 
---------------------------------------------------------------
-- RV01 PLIC gateway
---------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all; 
use IEEE.numeric_std.all;
 
library work;
use work.RV01_PLIC_PKG.all;
 
entity RV01_PLIC_GWAY is
  generic(
    TRIG_TYPE : PLIC_TRIG_TYPE := LEVEL;
    REQ_MAXCNT : natural := 16
  );
  port(
    CLK_i : in std_logic;
    RST_i : in std_logic;
    REQ_i : in std_logic;
    IS_i : in std_logic;
 
    IP_o : out std_logic
  );
end RV01_PLIC_GWAY;
 
architecture ARC of RV01_PLIC_GWAY is
 
  signal IP,IP_q : std_logic;
  signal REQ,REQ_q,REQ_EDGE : std_logic;
  signal REQ_CNT_q : natural range 0 to REQ_MAXCNT-1;
 
begin
 
  GL: if(TRIG_TYPE = LEVEL) generate
 
  process(IP_q,REQ_i,IS_i)
  begin
    if(IP_q = '0') then
      -- Set pending request register 
      IP <= REQ_i;
    elsif(IS_i = '1' and REQ_i = '0') then
      -- Pending request has been serviced,
      -- and there's no new request:
      -- clear pending request register 
      IP <= '0';
    else
      IP <= IP_q;
    end if;
  end process;
 
  end generate;
 
  GE: if(TRIG_TYPE = EDGE) generate
 
  -- REQ_i edge detector
 
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
      if(RST_i = '1') then
        REQ_q <= '0';
      else
        REQ_q <= REQ_i;
      end if;
    end if;
  end process;
 
  REQ_EDGE <= REQ_i and REQ_q;
 
  -- Pending request counter
 
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
      if(RST_i = '1') then
        REQ_CNT_q <= 0;
      elsif(REQ_EDGE = '1' and REQ_CNT_q < REQ_MAXCNT and IS_i = '0') then
        -- There's a new request and pending 
        -- one has not been serviced: increment count.
        REQ_CNT_q <= REQ_CNT_q + 1;
      elsif(REQ_EDGE = '0' and REQ_CNT_q > 0 and IS_i = '1') then
        -- There's no new request and pending one has
        -- ben serviced: decrement count.
        REQ_CNT_q <= REQ_CNT_q - 1;
      end if;
    end if;
  end process;
 
  IP <= '1' when (REQ_CNT_q > 0) else '0';
 
  end generate;
 
  -- Pending request register
 
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
      if(RST_i = '1') then
        IP_q <= '0';
      else
        IP_q <= IP;
      end if;
    end if;
  end process;
 
  IP_o <= IP_q;
 
end ARC;
 

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