Subversion Repositories rv01_riscv_core

-----------------------------------------------------------------
--                                                             --
-----------------------------------------------------------------
--                                                             --
-- Copyright (C) 2015 Stefano Tonello                          --
--                                                             --
-- This source file may be used and distributed without        --
-- restriction provided that this copyright statement is not   --
-- removed from the file and that any derivative work contains --
-- the original copyright notice and the associated disclaimer.--
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         --
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-----------------------------------------------------------------
 
---------------------------------------------------------
-- RV01 Pipeline eXecution logic 
---------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all; 
use IEEE.numeric_std.all;
 
library WORK;
use WORK.RV01_CONSTS_PKG.all;
use WORK.RV01_TYPES_PKG.all;
use work.RV01_IDEC_PKG.all;
use work.RV01_OP_PKG.all;
 
entity RV01_PXLOG is
  port(
    ID_INSTR0_i : in DEC_INSTR_T;
    ID_INSTR1_i : in DEC_INSTR_T;
    ID_V_i : in std_logic_vector(2-1 downto 0);
    ID_FWDE_i : in std_logic_vector(2-1 downto 0);
 
    PXE1_o : out std_logic
  );
end RV01_PXLOG;
 
architecture ARC of RV01_PXLOG is
 
  function dep_a(RMTCH,IDV,IXV : std_logic;IDI,IXI : DEC_INSTR_T)
    return std_logic is
  begin
    if(
      (RMTCH = '1') and (IDI.RRS1 = '1') and (IXI.WRD = '1')
    ) then
      return(IDV and IXV);
    else
      return('0');
    end if;
  end function;
 
  function dep_b(RMTCH,IDV,IXV : std_logic;IDI,IXI : DEC_INSTR_T)
    return std_logic is
  begin
    if(
      (RMTCH = '1') and (IDI.RRS2 = '1') and (IXI.WRD = '1')
    ) then
      return(IDV and IXV);
    else
      return('0');
    end if;
  end function;
 
  signal DATA_DEPA : std_logic;
  signal DATA_DEPB : std_logic;
  signal RMTCH_A_ID0 : std_logic;
  signal RMTCH_B_ID0 : std_logic;
  signal ST0 : std_logic;
  signal ST1 : std_logic;
 
begin
 
  ----------------------------------------------------
  -- General rules:
  ----------------------------------------------------
 
  -- Instruction #1 is executed if:
  -- 1) there's no data dependency from instruction #0 AND
  -- 2) it can be executed by pipeline "B" AND
  -- 3) instruction #0 is executed (in-order issue!).
 
  -- Condition #3 is actually checked by pipe stall
  -- logic.
 
  ----------------------------------------------------
 
  -- Register match flags
 
  -- ID instr. #0 vs. ID instr. #1 register match flags 
  -- (when a flag is asserted, there's a match between a
  -- register read by ID instruction #1 and the register
  -- written by ID instruction #0).
 
  RMTCH_A_ID0 <= '1' when (ID_INSTR1_i.RS1 = ID_INSTR0_i.RD) else '0';
  RMTCH_B_ID0 <= '1' when (ID_INSTR1_i.RS2 = ID_INSTR0_i.RD) else '0';
 
  ----------------------------------------------------
 
  -- Data dependence flags
 
  DATA_DEPA <=
    dep_a(RMTCH_A_ID0,ID_V_i(1),ID_V_i(1),ID_INSTR1_i,ID_INSTR0_i);
 
  DATA_DEPB <=
    dep_b(RMTCH_B_ID0,ID_V_i(1),ID_V_i(1),ID_INSTR1_i,ID_INSTR0_i);
 
 
  ----------------------------------------------------
 
  -- parallel execution (of instr. #1) flag
 
  PXE1_o <=
    not(DATA_DEPA or DATA_DEPB) and -- instr. #1 doesn't depend from #0
    not(ID_INSTR1_i.P0_ONLY); -- instr. #1 can execute on pipe #1
 
end;