Subversion Repositories rv01_riscv_core

-----------------------------------------------------------------
--                                                             --
-----------------------------------------------------------------
--                                                             --
-- Copyright (C) 2015 Stefano Tonello                          --
--                                                             --
-- This source file may be used and distributed without        --
-- restriction provided that this copyright statement is not   --
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-----------------------------------------------------------------
 
---------------------------------------------------------------
-- RV01 32x32 Register File
---------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
library work;
use work.RV01_CONSTS_PKG.all;
use work.RV01_TYPES_PKG.all;
 
entity RV01_REGFILE_32X32_2W is
  port(
    CLK_i : in std_logic;
    RA0_i : in RID_T;
    RA1_i : in RID_T;
    RA2_i : in RID_T;
    RA3_i : in RID_T;
    WA0_i : in RID_T;
    WA1_i : in RID_T;
    WE0_i : in std_logic;
    WE1_i : in std_logic;
    D0_i : in std_logic_vector(SDLEN-1 downto 0);
    D1_i : in std_logic_vector(SDLEN-1 downto 0);
 
    Q0_o : out std_logic_vector(SDLEN-1 downto 0);
    Q1_o : out std_logic_vector(SDLEN-1 downto 0);
    Q2_o : out std_logic_vector(SDLEN-1 downto 0);
    Q3_o : out std_logic_vector(SDLEN-1 downto 0)
  );
end RV01_REGFILE_32X32_2W;
 
architecture ARC of RV01_REGFILE_32X32_2W is
 
  subtype WORD_T is std_logic_vector(SDLEN-1 downto 0);
  type MEM_T is array (REGNUM-1 downto 0) of WORD_T;
 
  signal REG_q : MEM_T;
 
begin
 
  -- sync. write
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
      if(WE0_i = '1') then
        REG_q(WA0_i) <= D0_i;
      end if;
      if(WE1_i = '1') then
        REG_q(WA1_i) <= D1_i;
      end if;
    end if;
 
  end process;
 
  -- async. read
  Q0_o <= REG_q(RA0_i) when not(RA0_i = 0) else (others => '0');
  Q1_o <= REG_q(RA1_i) when not(RA1_i = 0) else (others => '0');
  Q2_o <= REG_q(RA2_i) when not(RA2_i = 0) else (others => '0');
  Q3_o <= REG_q(RA3_i) when not(RA3_i = 0) else (others => '0');
 
end ARC;