Subversion Repositories rv01_riscv_core

-----------------------------------------------------------------
--                                                             --
-----------------------------------------------------------------
--                                                             --
-- Copyright (C) 2016 Stefano Tonello                          --
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-- This source file may be used and distributed without        --
-- restriction provided that this copyright statement is not   --
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-----------------------------------------------------------------
 
---------------------------------------------------------------
-- RV01 result mux (IX1 stage)
---------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all; 
use IEEE.numeric_std.all;
 
library work;
use work.RV01_CONSTS_PKG.all;
use work.RV01_TYPES_PKG.all;
use work.RV01_IDEC_PKG.all;
 
entity RV01_RESMUX_IX1 is
  generic(
    PXE : std_logic := '1';
    DXE : std_logic := '1';
    NW : natural := 2
  );
  port(
    OPA0_V_i : in std_logic;
    OPA1_V_i : in std_logic;
    OPA0_i : in SDWORD_T;
    OPA1_i : in SDWORD_T;
    OPB0_V_i : in std_logic;
    OPB1_V_i : in std_logic;
    OPB0_i : in SDWORD_T;
    OPB1_i : in SDWORD_T;
    SHF_RES0_i : in SDWORD_T;
    SHF_RES1_i : in SDWORD_T;
    PA0_ALU_RES_i : in SDWORD_T;
    PA1_ALU_RES_i : in SDWORD_T;
    DIV_V_i : in std_logic;
    DIV_RES_i : in SDWORD_T;
    PASEL0_i : in std_logic_vector(4-1 downto 0);
    PASEL1_i : in std_logic_vector(4-1 downto 0);
    FWDE_i : in std_logic_vector(NW-1 downto 0);
    DSA0_i : in std_logic;
    DSB0_i : in std_logic;
    DSA1_i : in std_logic;
    DSB1_i : in std_logic;
    INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
    IX3_DRD0_i : in SDWORD_T;
    IX3_DRD1_i : in SDWORD_T;
    IX3_V_i : in std_logic_vector(NW-1 downto 0);
    IX3_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
 
    FWDX_o : out std_logic_vector(NW-1 downto 0);
    PA0_RES_o : out SDWORD_T;
    PA1_RES_o : out SDWORD_T;
    OPA0_V_o : out std_logic;
    OPA1_V_o : out std_logic;
    OPA0_o : out SDWORD_T;
    OPA1_o : out SDWORD_T;
    OPB0_V_o : out std_logic;
    OPB1_V_o : out std_logic;
    OPB0_o : out SDWORD_T;
    OPB1_o : out SDWORD_T;
    DRD0_V_o : out std_logic;
    DRD1_V_o : out std_logic;
    DRD0_o : out SDWORD_T;
    DRD1_o : out SDWORD_T
  );
end RV01_RESMUX_IX1;
 
architecture ARC of RV01_RESMUX_IX1 is
 
  component RV01_PIPE_A_RMX_X2 is
    generic(
      NW : natural := 2
    );
    port(
      OPA_V_i :  in std_logic;
      OPB_V_i :  in std_logic;
      OPA_i : in SDWORD_T;
      OPB_i : in SDWORD_T;
      INSTR_i : in DEC_INSTR_T;
      IX3_V_i : in std_logic_vector(NW-1 downto 0);
      IX3_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
      IX3_RES0_i : in SDWORD_T;
      IX3_RES1_i : in SDWORD_T;
 
      OPA_V_o :  out std_logic;
      OPB_V_o :  out std_logic;
      OPA_o : out SDWORD_T;
      OPB_o : out SDWORD_T
  );
  end component;
 
  signal PA0_RES : SDWORD_T;
  signal PA1_RES : SDWORD_T;
 
begin
 
  -------------------------------------------
  -- Delayed execution disabled
  -------------------------------------------
 
  PA0_RES <=
    SHF_RES0_i when(PASEL0_i(1) = '1') else
    PA0_ALU_RES_i;
 
  GPX_3_1 : if(PXE = '1') generate
 
  PA1_RES <=
    SHF_RES1_i when(PASEL1_i(1) = '1') else
    PA1_ALU_RES_i;
 
  end generate; -- GPX_3_1
 
  GPX_3_0 : if(PXE = '0') generate
 
 
  PA1_RES <= (others => '0');
 
  end generate; -- GPX_3_0
 
  PA0_RES_o <= PA0_RES;
 
  PA1_RES_o <= PA1_RES;
 
  GDX1_0 : if(DXE = '0') generate
 
  -- If delayed execution is not enabled, when pipe-A
  -- instructions reach IX1 stage their operand are
  -- already available and therefore they can safely
  -- executed and their result forwarded to ID stage.
 
  -- Result forwarding flags
  FWDX_o(0) <= FWDE_i(0);
  FWDX_o(1) <= FWDE_i(1) and DXE;
 
  -- Slot #0 instruction can be provided by pipe-A or by
  -- divider.
 
  DRD0_o <=
    DIV_RES_i when (DIV_V_i = '1') else
    PA0_RES;
 
  -- Slot #0 result valid flag
  DRD0_V_o <= '1' when (
    DIV_V_i = '1' or (
      PASEL0_i(0) = '1' or
      PASEL0_i(1) = '1' or
      PASEL0_i(2) = '1'
    )
  ) else '0';
 
  GPX_4_1 : if(PXE = '1') generate
 
  -- Slot #1 instruction can be provided by pipe-A only.
 
  DRD1_o <= PA1_RES;
 
  -- Slot #1 result valid flag
  DRD1_V_o <= '1' when (
    PASEL1_i(0) = '1' or
    PASEL1_i(1) = '1' or
    PASEL1_i(2) = '1'
  ) else '0';
 
  end generate; -- GPX_4_1
 
  GPX_4_0 : if(PXE = '0') generate
 
  DRD1_o <= (others => '0');
  DRD1_V_o <= '0';
 
  end generate; -- GPX_4_0
 
  OPA0_V_o <= '0';
  OPA1_V_o <= '0';
  OPA0_o <= (others => '0');
  OPA1_o <= (others => '0');
  OPB0_V_o <= '0';
  OPB1_V_o <= '0';
  OPB0_o <= (others => '0');
  OPB1_o <= (others => '0');
 
  end generate; -- GDX1_0
 
  -------------------------------------------
  -- Delayed execution enabled
  -------------------------------------------
 
  GDX1_1 : if(DXE = '1') generate
 
  -- If delayed execution is enabled, when pipe-A
  -- instructions reach IX1 stage their operand are
  -- available only if their valid bits are set.
 
  -- Note: IX1_PA*_RES are used for forwarding only!
 
  U_PA0RMX_X1: RV01_PIPE_A_RMX_X2
    generic map(
      NW => NW
    )
    port map(
      OPA_V_i => OPA0_V_i,
      OPB_V_i => OPB0_V_i,
      OPA_i => OPA0_i,
      OPB_i => OPB0_i,
      INSTR_i => INSTR_i(0),
      IX3_V_i => IX3_V_i,
      IX3_INSTR_i => IX3_INSTR_i,
      IX3_RES0_i => IX3_DRD0_i,
      IX3_RES1_i => IX3_DRD1_i,
 
      OPA_V_o => OPA0_V_o,
      OPB_V_o => OPB0_V_o,
      OPA_o => OPA0_o,
      OPB_o => OPB0_o
  );
 
  GPX_4_1 : if(PXE = '1') generate
 
  U_PA1RMX_X1: RV01_PIPE_A_RMX_X2
    generic map(
      NW => NW
    )
    port map(
      OPA_V_i => OPA1_V_i,
      OPB_V_i => OPB1_V_i,
      OPA_i => OPA1_i,
      OPB_i => OPB1_i,
      INSTR_i => INSTR_i(1),
      IX3_V_i => IX3_V_i,
      IX3_INSTR_i => IX3_INSTR_i,
      IX3_RES0_i => IX3_DRD0_i,
      IX3_RES1_i => IX3_DRD1_i,
 
      OPA_V_o => OPA1_V_o,
      OPB_V_o => OPB1_V_o,
      OPA_o => OPA1_o,
      OPB_o => OPB1_o
  );
 
  end generate; -- GPX_4_1
 
  GPX_4_0 : if(PXE = '0') generate
 
  OPA1_V_o <= '0';
  OPB1_V_o <= '0';
  OPA1_o <= (others => '0');
  OPB1_o <= (others => '0');
 
  end generate; -- GPX_4_0
 
  -- Result of instruction #0/1 is forwardable if
  -- instruction is of forwardable type and if
  -- both operands to ALU/SHFU are valid.
 
  FWDX_o(0) <= 
    FWDE_i(0) and 
    (OPA0_V_i and not(DSA0_i)) and 
    (OPB0_V_i and not(DSB0_i));
 
  FWDX_o(1) <= 
    FWDE_i(1) and 
    (OPA1_V_i and not(DSA1_i)) and 
    (OPB1_V_i and not(DSB1_i)) and
    PXE;
 
  -- Slot #0 instruction result can be provided
  -- by shifter or by divider.
 
  DRD0_o <= DIV_RES_i when (DIV_V_i = '1') else SHF_RES0_i;
 
  -- Slot #0 result valid flag
  DRD0_V_o <= '1' when (DIV_V_i = '1' or PASEL0_i(1) = '1') else '0';
 
  GPX_5_1 : if(PXE = '1') generate
 
  -- Slot #1 instruction result can be provided
  -- by shifter only.
 
  DRD1_o <= SHF_RES1_i;
 
  -- Slot #1 result valid flag
  DRD1_V_o <= '1' when (PASEL1_i(1) = '1') else '0';
 
  end generate; -- GPX_5_1
 
  GPX_5_0 : if(PXE = '0') generate
 
  DRD1_o <= (others => '0');
  DRD1_V_o <= '0';
 
  end generate; -- GPX_5_0
 
  end generate; -- GDX1_1
 
end ARC;