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[/] [rv01_riscv_core/] [trunk/] [VHDL/] [RV01_shftu.vhd] - Rev 2
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----------------------------------------------------------------- -- -- ----------------------------------------------------------------- -- -- -- Copyright (C) 2015 Stefano Tonello -- -- -- -- This source file may be used and distributed without -- -- restriction provided that this copyright statement is not -- -- removed from the file and that any derivative work contains -- -- the original copyright notice and the associated disclaimer.-- -- -- -- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- -- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- -- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- -- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- -- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- -- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- -- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- -- POSSIBILITY OF SUCH DAMAGE. -- -- -- ----------------------------------------------------------------- --------------------------------------------------------- -- RV01 shift unit --------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library WORK; use WORK.RV01_CONSTS_PKG.all; use WORK.RV01_TYPES_PKG.all; use WORK.RV01_FUNCS_PKG.all; use WORK.RV01_ARITH_PKG.all; entity RV01_SHFTU is port( CTRL_i : in SHF_CTRL; SI_i : in SDWORD_T; SHFT_i : in unsigned(5-1 downto 0); SU_i : in std_logic; SO_o : out SDWORD_T ); end RV01_SHFTU; architecture ARC of RV01_SHFTU is signal SHFT : SHORT_SHIFT_T; signal LSO : SDWORD_T; signal RSOS : SDWORD_T; signal RSOU : SDWORD_T; begin -- get shift amount SHFT <= to_integer(SHFT_i); -- 32-bit left shifter LSO <= shift_left32(SI_i,SHFT); -- 32-bit signed right shifter RSOS <= shift_right32(SI_i,SHFT); -- 32-bit unsigned right shifter RSOU <= to_signed(shift_right32(to_unsigned(SI_i),SHFT)); SO_o <= LSO when (CTRL_i = SC_SHL) else RSOS when (CTRL_i = SC_SHR and SU_i = '1') else RSOU; end ARC;