Subversion Repositories rv01_riscv_core

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--                                                             --
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--                                                             --
-- Copyright (C) 2015 Stefano Tonello                          --
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---------------------------------------------------------------
-- RV01 constants package
---------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all; 
use IEEE.numeric_std.all;
 
library WORK;
use WORK.RV01_CONSTS_PKG.all;
 
package RV01_TYPES_PKG is
 
  -- short (signed) data word type
  subtype SDWORD_T is signed(SDLEN-1 downto 0);
 
  -- long (signed) data word type
  subtype LDWORD_T is signed(LDLEN-1 downto 0);
 
  -- short unsigned data word type
  subtype SDWORDU_T is unsigned(SDLEN-1 downto 0);
 
  -- long unsigned data word type
  subtype LDWORDU_T is unsigned(LDLEN-1 downto 0);
 
  -- register identifier type
  subtype RID_T is integer range 0 to REGNUM-1;
 
  -- short shift amount type
  subtype SHORT_SHIFT_T is integer range 0 to SDLEN-1;
 
  -- long shift amount type
  subtype LONG_SHIFT_T is integer range 0 to LDLEN-1;
 
  subtype ADR_T is unsigned(ALEN-1 downto 0);
 
  type SDWORD_VEC_T is array (natural range<>) of SDWORD_T;
 
  type LDWORD_VEC_T is array (natural range<>) of LDWORD_T;
 
  type ADR_VEC_T is array (natural range<>) of ADR_T;
 
end package;
 
package body RV01_TYPES_PKG is
end package body;