Subversion Repositories rv01_riscv_core

-----------------------------------------------------------------
--                                                             --
-----------------------------------------------------------------
--                                                             --
-- Copyright (C) 2015 Stefano Tonello                          --
--                                                             --
-- This source file may be used and distributed without        --
-- restriction provided that this copyright statement is not   --
-- removed from the file and that any derivative work contains --
-- the original copyright notice and the associated disclaimer.--
--                                                             --
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY         --
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   --
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   --
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      --
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         --
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    --
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   --
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        --
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  --
-- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  --
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  --
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         --
-- POSSIBILITY OF SUCH DAMAGE.                                 --
--                                                             --
-----------------------------------------------------------------
 
---------------------------------------------------------------
-- RV01 configuration package ("C" core version)
---------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
library work;
use work.RV01_CONSTS_PKG.all;
use work.RV01_TYPES_PKG.all;
use WORK.RV01_FUNCS_PKG.all;
use WORK.RV01_PLIC_PKG.all;
 
package RV01_CFG_PKG is
 
  -- Pay attention: these values make reference to 32-bit
  -- words, not to bytes (for instance, actual instruction
  -- memory address range is [0:IMEM_SIZE*4-1]).
 
  constant ASPC_SIZE : natural := 1024*64; -- 256Kb
  constant IMEM_SIZE : natural := 1024*32; -- 128Kb
  constant DMEM_SIZE : natural := 1024*12; -- 48Kb -- 64Kb for syn.
  constant IOMEM_SIZE : natural := 0; -- 0Kb (no I/O mem.)
 
  constant IMEM_SIZE_PO2 : std_logic := '1';
  constant DMEM_SIZE_PO2 : std_logic := '0';
 
  constant IMEM_LOWM : std_logic := '1';
 
  constant PARALLEL_EXECUTION_ENABLED : std_logic := '1';
  constant DELAYED_EXECUTION_ENABLED : std_logic := '1';
  constant BRANCH_PREDICTION_ENABLED : std_logic := '1';
  constant JALR_PREDICTION_ENABLED : std_logic := '1';
  constant FPU_PRESENT : std_logic := '0';
  constant DM_PRESENT : std_logic := '0';
  constant PLIC_PRESENT : std_logic := '0';
 
  -- Branch History Table size
  -- (this paramter makes sense only if BRANCH_PREDICTION_ENABLED = '1')
  constant BHT_SIZE : natural := 256;
 
  -- PLIC parameters (PLIC_PRESENT must be = '1')
  constant EI_SRC_CNT : natural := 1;
  constant EI_TRIG_TYPE : PLIC_TRIG_TYPE := LEVEL;
  constant EI_REQ_MAXCNT : natural := 0;
 
end package;
 
package body RV01_CFG_PKG is
end package body;