Subversion Repositories s1_core

analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/behav/sparc_libs/u1_lib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/behav/sparc_libs/m1_lib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mamul.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mast.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_pib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_madp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_maaeqb.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mared.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cluster_header.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mactl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_wen.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mald.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_maaddr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_lsurpt.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_maexp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_lsurpt1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/mul64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/s1_top/rst_ctrl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/s1_top/int_ctrl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/s1_top/spc2wbm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/s1_top/s1_top.v
# The Tcl script under $S1_ROOT/tools/src/build_dc.cmd is attached at the end of the filelist for DC;
# if you modify this file *REMEMBER* to run 'update_filelist' or you'll run the old version!!!

elaborate s1_top
link
uniquify
check_design

# Constraints

create_clock -name "sys_clock_i" -period 2.0 -waveform {0 1.0} [get_ports "sys_clock_i"]
set_dont_touch_network [get_clocks "sys_clock_i"]
set_input_delay 1.25 -max -rise -clock "sys_clock_i" [get_ports "sys_reset_i"]
set_input_delay 1.25 -max -fall -clock "sys_clock_i" [get_ports "sys_reset_i"]
set_output_delay 1.25 -clock sys_clock_i -max -rise [all_outputs]
set_output_delay 1.25 -clock sys_clock_i -max -fall [all_outputs]
set_wire_load_mode "enclosed" 

# Compile

compile

# Export

write -format db -hierarchy -output "s1_top.db"
write -format verilog -hierarchy -output "s1_top.v"

# Report

report_area > report_area.txt
report_timing > report_timing.txt
report_constraint -all_violators > report_constraint.txt

quit