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// ========== Copyright Header Begin ========================================== // // OpenSPARC T1 Processor File: u1.behV // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. // // The above named program is free software; you can redistribute it and/or // modify it under the terms of the GNU General Public // License version 2 as published by the Free Software Foundation. // // The above named program is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU // General Public License for more details. // // You should have received a copy of the GNU General Public // License along with this work; if not, write to the Free Software // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. // // ========== Copyright Header End ============================================ //////////////////////////////////////////////////////////////////////// // // basic gates { // //////////////////////////////////////////////////////////////////////// `ifndef SIMPLY_RISC_TWEAKS //bw_u1_inv_0p6x // // module bw_u1_inv_0p6x ( z, a ); output z; input a; assign z = ~( a ); endmodule //bw_u1_inv_1x // // module bw_u1_inv_1x ( z, a ); output z; input a; assign z = ~( a ); endmodule //bw_u1_inv_1p4x // // module bw_u1_inv_1p4x ( z, a ); output z; input a; assign z = ~( a ); endmodule //bw_u1_inv_2x // // module bw_u1_inv_2x ( z, a ); output z; input a; assign z = ~( a ); endmodule //bw_u1_inv_3x // // module bw_u1_inv_3x ( z, a ); output z; input a; assign z = ~( a ); endmodule //bw_u1_inv_4x // // module bw_u1_inv_4x ( z, a ); output z; input a; assign z = ~( a ); endmodule //bw_u1_inv_5x // // module bw_u1_inv_5x ( z, a ); output z; input a; assign z = ~( a ); endmodule `endif //bw_u1_inv_8x // // module bw_u1_inv_8x ( z, a ); output z; input a; assign z = ~( a ); endmodule //bw_u1_inv_10x // // module bw_u1_inv_10x ( z, a ); output z; input a; assign z = ~( a ); endmodule //bw_u1_inv_15x // // module bw_u1_inv_15x ( z, a ); output z; input a; assign z = ~( a ); endmodule //bw_u1_inv_20x // // module bw_u1_inv_20x ( z, a ); output z; input a; assign z = ~( a ); endmodule //bw_u1_inv_30x // // module bw_u1_inv_30x ( z, a ); output z; input a; assign z = ~( a ); endmodule `ifndef SIMPLY_RISC_TWEAKS //bw_u1_inv_40x // // module bw_u1_inv_40x ( z, a ); output z; input a; assign z = ~( a ); endmodule //bw_u1_invh_15x // // module bw_u1_invh_15x ( z, a ); output z; input a; assign z = ~( a ); endmodule //bw_u1_invh_25x // // module bw_u1_invh_25x ( z, a ); output z; input a; assign z = ~( a ); endmodule //bw_u1_invh_30x // // module bw_u1_invh_30x ( z, a ); output z; input a; assign z = ~( a ); endmodule //bw_u1_invh_50x // // module bw_u1_invh_50x ( z, a ); output z; input a; assign z = ~( a ); endmodule //bw_u1_invh_60x // // module bw_u1_invh_60x ( z, a ); output z; input a; assign z = ~( a ); endmodule //bw_u1_nand2_0p4x // // module bw_u1_nand2_0p4x ( z, a, b ); output z; input a; input b; assign z = ~( a & b ); endmodule //bw_u1_nand2_0p6x // // module bw_u1_nand2_0p6x ( z, a, b ); output z; input a; input b; assign z = ~( a & b ); endmodule //bw_u1_nand2_1x // // module bw_u1_nand2_1x ( z, a, b ); output z; input a; input b; assign z = ~( a & b ); endmodule //bw_u1_nand2_1p4x // // module bw_u1_nand2_1p4x ( z, a, b ); output z; input a; input b; assign z = ~( a & b ); endmodule `endif //bw_u1_nand2_2x // // module bw_u1_nand2_2x ( z, a, b ); output z; input a; input b; assign z = ~( a & b ); endmodule `ifndef SIMPLY_RISC_TWEAKS //bw_u1_nand2_3x // // module bw_u1_nand2_3x ( z, a, b ); output z; input a; input b; assign z = ~( a & b ); endmodule `endif //bw_u1_nand2_4x // // module bw_u1_nand2_4x ( z, a, b ); output z; input a; input b; assign z = ~( a & b ); endmodule `ifndef SIMPLY_RISC_TWEAKS //bw_u1_nand2_5x // // module bw_u1_nand2_5x ( z, a, b ); output z; input a; input b; assign z = ~( a & b ); endmodule //bw_u1_nand2_7x // // module bw_u1_nand2_7x ( z, a, b ); output z; input a; input b; assign z = ~( a & b ); endmodule `endif //bw_u1_nand2_10x // // module bw_u1_nand2_10x ( z, a, b ); output z; input a; input b; assign z = ~( a & b ); endmodule //bw_u1_nand2_15x // // module bw_u1_nand2_15x ( z, a, b ); output z; input a; input b; assign z = ~( a & b ); endmodule `ifndef SIMPLY_RISC_TWEAKS //bw_u1_nand3_0p4x // // module bw_u1_nand3_0p4x ( z, a, b, c ); output z; input a; input b; input c; assign z = ~( a & b & c ); endmodule //bw_u1_nand3_0p6x // // module bw_u1_nand3_0p6x ( z, a, b, c ); output z; input a; input b; input c; assign z = ~( a & b & c ); endmodule //bw_u1_nand3_1x // // module bw_u1_nand3_1x ( z, a, b, c ); output z; input a; input b; input c; assign z = ~( a & b & c ); endmodule //bw_u1_nand3_1p4x // // module bw_u1_nand3_1p4x ( z, a, b, c ); output z; input a; input b; input c; assign z = ~( a & b & c ); endmodule //bw_u1_nand3_2x // // module bw_u1_nand3_2x ( z, a, b, c ); output z; input a; input b; input c; assign z = ~( a & b & c ); endmodule //bw_u1_nand3_3x // // module bw_u1_nand3_3x ( z, a, b, c ); output z; input a; input b; input c; assign z = ~( a & b & c ); endmodule `endif //bw_u1_nand3_4x // // module bw_u1_nand3_4x ( z, a, b, c ); output z; input a; input b; input c; assign z = ~( a & b & c ); endmodule `ifndef SIMPLY_RISC_TWEAKS //bw_u1_nand3_5x // // module bw_u1_nand3_5x ( z, a, b, c ); output z; input a; input b; input c; assign z = ~( a & b & c ); endmodule //bw_u1_nand3_7x // // module bw_u1_nand3_7x ( z, a, b, c ); output z; input a; input b; input c; assign z = ~( a & b & c ); endmodule //bw_u1_nand3_10x // // module bw_u1_nand3_10x ( z, a, b, c ); output z; input a; input b; input c; assign z = ~( a & b & c ); endmodule //bw_u1_nand4_0p6x // // module bw_u1_nand4_0p6x ( z, a, b, c, d ); output z; input a; input b; input c; input d; assign z = ~( a & b & c & d ); endmodule //bw_u1_nand4_1x // // module bw_u1_nand4_1x ( z, a, b, c, d ); output z; input a; input b; input c; input d; assign z = ~( a & b & c & d ); endmodule //bw_u1_nand4_1p4x // // module bw_u1_nand4_1p4x ( z, a, b, c, d ); output z; input a; input b; input c; input d; assign z = ~( a & b & c & d ); endmodule //bw_u1_nand4_2x // // module bw_u1_nand4_2x ( z, a, b, c, d ); output z; input a; input b; input c; input d; assign z = ~( a & b & c & d ); endmodule //bw_u1_nand4_3x // // module bw_u1_nand4_3x ( z, a, b, c, d ); output z; input a; input b; input c; input d; assign z = ~( a & b & c & d ); endmodule //bw_u1_nand4_4x // // module bw_u1_nand4_4x ( z, a, b, c, d ); output z; input a; input b; input c; input d; assign z = ~( a & b & c & d ); endmodule //bw_u1_nand4_6x // // module bw_u1_nand4_6x ( z, a, b, c, d ); output z; input a; input b; input c; input d; nand( z, a, b,c,d); endmodule //bw_u1_nand4_8x // // module bw_u1_nand4_8x ( z, a, b, c, d ); output z; input a; input b; input c; input d; nand( z, a, b,c,d); endmodule //bw_u1_nor2_0p6x // // module bw_u1_nor2_0p6x ( z, a, b ); output z; input a; input b; assign z = ~( a | b ); endmodule //bw_u1_nor2_1x // // module bw_u1_nor2_1x ( z, a, b ); output z; input a; input b; assign z = ~( a | b ); endmodule //bw_u1_nor2_1p4x // // module bw_u1_nor2_1p4x ( z, a, b ); output z; input a; input b; assign z = ~( a | b ); endmodule //bw_u1_nor2_2x // // module bw_u1_nor2_2x ( z, a, b ); output z; input a; input b; assign z = ~( a | b ); endmodule //bw_u1_nor2_3x // // module bw_u1_nor2_3x ( z, a, b ); output z; input a; input b; assign z = ~( a | b ); endmodule //bw_u1_nor2_4x // // module bw_u1_nor2_4x ( z, a, b ); output z; input a; input b; assign z = ~( a | b ); endmodule //bw_u1_nor2_6x // // module bw_u1_nor2_6x ( z, a, b ); output z; input a; input b; assign z = ~( a | b ); endmodule //bw_u1_nor2_8x // // module bw_u1_nor2_8x ( z, a, b ); output z; input a; input b; assign z = ~( a | b ); endmodule //bw_u1_nor2_12x // // module bw_u1_nor2_12x ( z, a, b ); output z; input a; input b; assign z = ~( a | b ); endmodule //bw_u1_nor3_0p6x // // module bw_u1_nor3_0p6x ( z, a, b, c ); output z; input a; input b; input c; assign z = ~( a | b | c ); endmodule //bw_u1_nor3_1x // // module bw_u1_nor3_1x ( z, a, b, c ); output z; input a; input b; input c; assign z = ~( a | b | c ); endmodule //bw_u1_nor3_1p4x // // module bw_u1_nor3_1p4x ( z, a, b, c ); output z; input a; input b; input c; assign z = ~( a | b | c ); endmodule //bw_u1_nor3_2x // // module bw_u1_nor3_2x ( z, a, b, c ); output z; input a; input b; input c; assign z = ~( a | b | c ); endmodule //bw_u1_nor3_3x // // module bw_u1_nor3_3x ( z, a, b, c ); output z; input a; input b; input c; assign z = ~( a | b | c ); endmodule //bw_u1_nor3_4x // // module bw_u1_nor3_4x ( z, a, b, c ); output z; input a; input b; input c; assign z = ~( a | b | c ); endmodule //bw_u1_nor3_6x // // module bw_u1_nor3_6x ( z, a, b, c ); output z; input a; input b; input c; assign z = ~( a | b | c ); endmodule `endif //bw_u1_nor3_8x // // module bw_u1_nor3_8x ( z, a, b, c ); output z; input a; input b; input c; assign z = ~( a | b | c ); endmodule `ifndef SIMPLY_RISC_TWEAKS //bw_u1_aoi21_0p4x // // module bw_u1_aoi21_0p4x ( z, b1, b2, a ); output z; input b1; input b2; input a; assign z = ~(( b1 & b2 ) | ( a )); endmodule //bw_u1_aoi21_1x // // module bw_u1_aoi21_1x ( z, b1, b2, a ); output z; input b1; input b2; input a; assign z = ~(( b1 & b2 ) | ( a )); endmodule //bw_u1_aoi21_2x // // module bw_u1_aoi21_2x ( z, b1, b2, a ); output z; input b1; input b2; input a; assign z = ~(( b1 & b2 ) | ( a )); endmodule `endif //bw_u1_aoi21_4x // // module bw_u1_aoi21_4x ( z, b1, b2, a ); output z; input b1; input b2; input a; assign z = ~(( b1 & b2 ) | ( a )); endmodule `ifndef SIMPLY_RISC_TWEAKS //bw_u1_aoi21_8x // // module bw_u1_aoi21_8x ( z, b1, b2, a ); output z; input b1; input b2; input a; assign z = ~(( b1 & b2 ) | ( a )); endmodule //bw_u1_aoi21_12x // // module bw_u1_aoi21_12x ( z, b1, b2, a ); output z; input b1; input b2; input a; assign z = ~(( b1 & b2 ) | ( a )); endmodule //bw_u1_aoi22_0p4x // // module bw_u1_aoi22_0p4x ( z, a1, a2, b1, b2 ); output z; input a1; input a2; input b1; input b2; assign z = ~(( a1 & a2 ) | ( b1 & b2 )); endmodule //bw_u1_aoi22_1x // // module bw_u1_aoi22_1x ( z, b1, b2, a1, a2 ); output z; input b1; input b2; input a1; input a2; assign z = ~(( a1 & a2 ) | ( b1 & b2 )); endmodule `endif //bw_u1_aoi22_2x // // module bw_u1_aoi22_2x ( z, b1, b2, a1, a2 ); output z; input b1; input b2; input a1; input a2; assign z = ~(( a1 & a2 ) | ( b1 & b2 )); endmodule `ifndef SIMPLY_RISC_TWEAKS //bw_u1_aoi22_4x // // module bw_u1_aoi22_4x ( z, b1, b2, a1, a2 ); output z; input b1; input b2; input a1; input a2; assign z = ~(( a1 & a2 ) | ( b1 & b2 )); endmodule //bw_u1_aoi22_8x // // module bw_u1_aoi22_8x ( z, b1, b2, a1, a2 ); output z; input b1; input b2; input a1; input a2; assign z = ~(( a1 & a2 ) | ( b1 & b2 )); endmodule //bw_u1_aoi211_0p3x // // module bw_u1_aoi211_0p3x ( z, c1, c2, b, a ); output z; input c1; input c2; input b; input a; assign z = ~(( c1 & c2 ) | (a)| (b)); endmodule //bw_u1_aoi211_1x // // module bw_u1_aoi211_1x ( z, c1, c2, b, a ); output z; input c1; input c2; input b; input a; assign z = ~(( c1 & c2 ) | (a)| (b)); endmodule //bw_u1_aoi211_2x // // module bw_u1_aoi211_2x ( z, c1, c2, b, a ); output z; input c1; input c2; input b; input a; assign z = ~(( c1 & c2 ) | (a)| (b)); endmodule //bw_u1_aoi211_4x // // module bw_u1_aoi211_4x ( z, c1, c2, b, a ); output z; input c1; input c2; input b; input a; assign z = ~(( c1 & c2 ) | (a)| (b)); endmodule //bw_u1_aoi211_8x // // module bw_u1_aoi211_8x ( z, c1, c2, b, a ); output z; input c1; input c2; input b; input a; assign z = ~(( c1 & c2 ) | (a)| (b)); endmodule //bw_u1_oai21_0p4x // // module bw_u1_oai21_0p4x ( z, b1, b2, a ); output z; input b1; input b2; input a; assign z = ~(( b1 | b2 ) & ( a )); endmodule //bw_u1_oai21_1x // // module bw_u1_oai21_1x ( z, b1, b2, a ); output z; input b1; input b2; input a; assign z = ~(( b1 | b2 ) & ( a )); endmodule //bw_u1_oai21_2x // // module bw_u1_oai21_2x ( z, b1, b2, a ); output z; input b1; input b2; input a; assign z = ~(( b1 | b2 ) & ( a )); endmodule //bw_u1_oai21_4x // // module bw_u1_oai21_4x ( z, b1, b2, a ); output z; input b1; input b2; input a; assign z = ~(( b1 | b2 ) & ( a )); endmodule //bw_u1_oai21_8x // // module bw_u1_oai21_8x ( z, b1, b2, a ); output z; input b1; input b2; input a; assign z = ~(( b1 | b2 ) & ( a )); endmodule //bw_u1_oai21_12x // // module bw_u1_oai21_12x ( z, b1, b2, a ); output z; input b1; input b2; input a; assign z = ~(( b1 | b2 ) & ( a )); endmodule //bw_u1_oai22_0p4x // module bw_u1_oai22_0p4x ( z, a1, a2, b1, b2 ); output z; input a1; input a2; input b1; input b2; assign z = ~(( a1 | a2 ) & ( b1 | b2 )); endmodule //bw_u1_oai22_1x // module bw_u1_oai22_1x ( z, a1, a2, b1, b2 ); output z; input a1; input a2; input b1; input b2; assign z = ~(( a1 | a2 ) & ( b1 | b2 )); endmodule //bw_u1_oai22_2x // module bw_u1_oai22_2x ( z, a1, a2, b1, b2 ); output z; input a1; input a2; input b1; input b2; assign z = ~(( a1 | a2 ) & ( b1 | b2 )); endmodule //bw_u1_oai22_4x // module bw_u1_oai22_4x ( z, a1, a2, b1, b2 ); output z; input a1; input a2; input b1; input b2; assign z = ~(( a1 | a2 ) & ( b1 | b2 )); endmodule //bw_u1_oai22_8x // module bw_u1_oai22_8x ( z, a1, a2, b1, b2 ); output z; input a1; input a2; input b1; input b2; assign z = ~(( a1 | a2 ) & ( b1 | b2 )); endmodule //bw_u1_oai211_0p3x // // module bw_u1_oai211_0p3x ( z, c1, c2, b, a ); output z; input c1; input c2; input b; input a; assign z = ~(( c1 | c2 ) & ( a ) & (b)); endmodule //bw_u1_oai211_1x // // module bw_u1_oai211_1x ( z, c1, c2, b, a ); output z; input c1; input c2; input b; input a; assign z = ~(( c1 | c2 ) & ( a ) & (b)); endmodule //bw_u1_oai211_2x // // module bw_u1_oai211_2x ( z, c1, c2, b, a ); output z; input c1; input c2; input b; input a; assign z = ~(( c1 | c2 ) & ( a ) & (b)); endmodule //bw_u1_oai211_4x // // module bw_u1_oai211_4x ( z, c1, c2, b, a ); output z; input c1; input c2; input b; input a; assign z = ~(( c1 | c2 ) & ( a ) & (b)); endmodule //bw_u1_oai211_8x // // module bw_u1_oai211_8x ( z, c1, c2, b, a ); output z; input c1; input c2; input b; input a; assign z = ~(( c1 | c2 ) & ( a ) & (b)); endmodule //bw_u1_aoi31_1x // // module bw_u1_aoi31_1x ( z, b1, b2, b3, a ); output z; input b1; input b2; input b3; input a; assign z = ~(( b1 & b2&b3 ) | ( a )); endmodule //bw_u1_aoi31_2x // // module bw_u1_aoi31_2x ( z, b1, b2, b3, a ); output z; input b1; input b2; input b3; input a; assign z = ~(( b1 & b2&b3 ) | ( a )); endmodule //bw_u1_aoi31_4x // // module bw_u1_aoi31_4x ( z, b1, b2, b3, a ); output z; input b1; input b2; input b3; input a; assign z = ~(( b1 & b2&b3 ) | ( a )); endmodule //bw_u1_aoi31_8x // // module bw_u1_aoi31_8x ( z, b1, b2, b3, a ); output z; input b1; input b2; input b3; input a; assign z = ~(( b1 & b2&b3 ) | ( a )); endmodule //bw_u1_aoi32_1x // // module bw_u1_aoi32_1x ( z, b1, b2, b3, a1, a2 ); output z; input b1; input b2; input b3; input a1; input a2; assign z = ~(( b1 & b2&b3 ) | ( a1 & a2 )); endmodule //bw_u1_aoi32_2x // // module bw_u1_aoi32_2x ( z, b1, b2, b3, a1, a2 ); output z; input b1; input b2; input b3; input a1; input a2; assign z = ~(( b1 & b2&b3 ) | ( a1 & a2 )); endmodule //bw_u1_aoi32_4x // // module bw_u1_aoi32_4x ( z, b1, b2, b3, a1, a2 ); output z; input b1; input b2; input b3; input a1; input a2; assign z = ~(( b1 & b2&b3 ) | ( a1 & a2 )); endmodule //bw_u1_aoi32_8x // // module bw_u1_aoi32_8x ( z, b1, b2, b3, a1, a2 ); output z; input b1; input b2; input b3; input a1; input a2; assign z = ~(( b1 & b2&b3 ) | ( a1 & a2 )); endmodule //bw_u1_aoi33_1x // // module bw_u1_aoi33_1x ( z, b1, b2, b3, a1, a2, a3 ); output z; input b1; input b2; input b3; input a1; input a2; input a3; assign z = ~(( b1 & b2&b3 ) | ( a1&a2&a3 )); endmodule //bw_u1_aoi33_2x // // module bw_u1_aoi33_2x ( z, b1, b2, b3, a1, a2, a3 ); output z; input b1; input b2; input b3; input a1; input a2; input a3; assign z = ~(( b1 & b2&b3 ) | ( a1&a2&a3 )); endmodule //bw_u1_aoi33_4x // // module bw_u1_aoi33_4x ( z, b1, b2, b3, a1, a2, a3 ); output z; input b1; input b2; input b3; input a1; input a2; input a3; assign z = ~(( b1 & b2&b3 ) | ( a1&a2&a3 )); endmodule //bw_u1_aoi33_8x // // module bw_u1_aoi33_8x ( z, b1, b2, b3, a1, a2, a3 ); output z; input b1; input b2; input b3; input a1; input a2; input a3; assign z = ~(( b1 & b2&b3 ) | ( a1&a2&a3 )); endmodule //bw_u1_aoi221_1x // // module bw_u1_aoi221_1x ( z, c1, c2, b1, b2, a ); output z; input c1; input c2; input b1; input b2; input a; assign z = ~(( c1 & c2 ) | (b1&b2)| (a)); endmodule //bw_u1_aoi221_2x // // module bw_u1_aoi221_2x ( z, c1, c2, b1, b2, a ); output z; input c1; input c2; input b1; input b2; input a; assign z = ~(( c1 & c2 ) | (b1&b2)| (a)); endmodule //bw_u1_aoi221_4x // // module bw_u1_aoi221_4x ( z, c1, c2, b1, b2, a ); output z; input c1; input c2; input b1; input b2; input a; assign z = ~(( c1 & c2 ) | (b1&b2)| (a)); endmodule //bw_u1_aoi221_8x // // module bw_u1_aoi221_8x ( z, c1, c2, b1, b2, a ); output z; input c1; input c2; input b1; input b2; input a; assign z = ~(( c1 & c2 ) | (b1&b2)| (a)); endmodule //bw_u1_aoi222_1x // // module bw_u1_aoi222_1x ( z, a1, a2, b1, b2, c1, c2 ); output z; input a1; input a2; input b1; input b2; input c1; input c2; assign z = ~(( c1 & c2 ) | (b1&b2)| (a1& a2)); endmodule //bw_u1_aoi222_2x // // module bw_u1_aoi222_2x ( z, a1, a2, b1, b2, c1, c2 ); output z; input a1; input a2; input b1; input b2; input c1; input c2; assign z = ~(( c1 & c2 ) | (b1&b2)| (a1& a2)); endmodule //bw_u1_aoi222_4x // // module bw_u1_aoi222_4x ( z, a1, a2, b1, b2, c1, c2 ); output z; input a1; input a2; input b1; input b2; input c1; input c2; assign z = ~(( c1 & c2 ) | (b1&b2)| (a1& a2)); endmodule //bw_u1_aoi311_1x // // module bw_u1_aoi311_1x ( z, c1, c2, c3, b, a ); output z; input c1; input c2; input c3; input b; input a; assign z = ~(( c1 & c2& c3 ) | (a)| (b)); endmodule //bw_u1_aoi311_2x // // module bw_u1_aoi311_2x ( z, c1, c2, c3, b, a ); output z; input c1; input c2; input c3; input b; input a; assign z = ~(( c1 & c2& c3 ) | (a)| (b)); endmodule //bw_u1_aoi311_4x // // module bw_u1_aoi311_4x ( z, c1, c2, c3, b, a ); output z; input c1; input c2; input c3; input b; input a; assign z = ~(( c1 & c2& c3 ) | (a)| (b)); endmodule //bw_u1_aoi311_8x // // module bw_u1_aoi311_8x ( z, c1, c2, c3, b, a ); output z; input c1; input c2; input c3; input b; input a; assign z = ~(( c1 & c2& c3 ) | (a)| (b)); endmodule //bw_u1_oai31_1x // // module bw_u1_oai31_1x ( z, b1, b2, b3, a ); output z; input b1; input b2; input b3; input a; assign z = ~(( b1 | b2|b3 ) & ( a )); endmodule //bw_u1_oai31_2x // // module bw_u1_oai31_2x ( z, b1, b2, b3, a ); output z; input b1; input b2; input b3; input a; assign z = ~(( b1 | b2|b3 ) & ( a )); endmodule //bw_u1_oai31_4x // // module bw_u1_oai31_4x ( z, b1, b2, b3, a ); output z; input b1; input b2; input b3; input a; assign z = ~(( b1 | b2|b3 ) & ( a )); endmodule //bw_u1_oai31_8x // // module bw_u1_oai31_8x ( z, b1, b2, b3, a ); output z; input b1; input b2; input b3; input a; assign z = ~(( b1 | b2|b3 ) & ( a )); endmodule //bw_u1_oai32_1x // // module bw_u1_oai32_1x ( z, b1, b2, b3, a1, a2 ); output z; input b1; input b2; input b3; input a1; input a2; assign z = ~(( b1 | b2 | b3 ) & ( a1 | a2 )); endmodule //bw_u1_oai32_2x // // module bw_u1_oai32_2x ( z, b1, b2, b3, a1, a2 ); output z; input b1; input b2; input b3; input a1; input a2; assign z = ~(( b1 | b2 | b3 ) & ( a1 | a2 )); endmodule //bw_u1_oai32_4x // // module bw_u1_oai32_4x ( z, b1, b2, b3, a1, a2 ); output z; input b1; input b2; input b3; input a1; input a2; assign z = ~(( b1 | b2 | b3 ) & ( a1 | a2 )); endmodule //bw_u1_oai32_8x // // module bw_u1_oai32_8x ( z, b1, b2, b3, a1, a2 ); output z; input b1; input b2; input b3; input a1; input a2; assign z = ~(( b1 | b2 | b3 ) & ( a1 | a2 )); endmodule //bw_u1_oai33_1x // // module bw_u1_oai33_1x ( z, b1, b2, b3, a1, a2, a3 ); output z; input b1; input b2; input b3; input a1; input a2; input a3; assign z = ~(( b1 | b2|b3 ) & ( a1|a2|a3 )); endmodule //bw_u1_oai33_2x // // module bw_u1_oai33_2x ( z, b1, b2, b3, a1, a2, a3 ); output z; input b1; input b2; input b3; input a1; input a2; input a3; assign z = ~(( b1 | b2|b3 ) & ( a1|a2|a3 )); endmodule //bw_u1_oai33_4x // // module bw_u1_oai33_4x ( z, b1, b2, b3, a1, a2, a3 ); output z; input b1; input b2; input b3; input a1; input a2; input a3; assign z = ~(( b1 | b2|b3 ) & ( a1|a2|a3 )); endmodule //bw_u1_oai33_8x // // module bw_u1_oai33_8x ( z, b1, b2, b3, a1, a2, a3 ); output z; input b1; input b2; input b3; input a1; input a2; input a3; assign z = ~(( b1 | b2|b3 ) & ( a1|a2|a3 )); endmodule //bw_u1_oai221_1x // // module bw_u1_oai221_1x ( z, c1, c2, b1, b2, a ); output z; input c1; input c2; input b1; input b2; input a; assign z = ~(( c1 | c2 ) & ( a ) & (b1|b2)); endmodule //bw_u1_oai221_2x // // module bw_u1_oai221_2x ( z, c1, c2, b1, b2, a ); output z; input c1; input c2; input b1; input b2; input a; assign z = ~(( c1 | c2 ) & ( a ) & (b1|b2)); endmodule //bw_u1_oai221_4x // // module bw_u1_oai221_4x ( z, c1, c2, b1, b2, a ); output z; input c1; input c2; input b1; input b2; input a; assign z = ~(( c1 | c2 ) & ( a ) & (b1|b2)); endmodule //bw_u1_oai221_8x // // module bw_u1_oai221_8x ( z, c1, c2, b1, b2, a ); output z; input c1; input c2; input b1; input b2; input a; assign z = ~(( c1 | c2 ) & ( a ) & (b1|b2)); endmodule //bw_u1_oai222_1x // // module bw_u1_oai222_1x ( z, c1, c2, b1, b2, a1, a2 ); output z; input c1; input c2; input b1; input b2; input a1; input a2; assign z = ~(( c1 | c2 ) & ( a1|a2 ) & (b1|b2)); endmodule //bw_u1_oai222_2x // // module bw_u1_oai222_2x ( z, c1, c2, b1, b2, a1, a2 ); output z; input c1; input c2; input b1; input b2; input a1; input a2; assign z = ~(( c1 | c2 ) & ( a1|a2 ) & (b1|b2)); endmodule //bw_u1_oai222_4x // // module bw_u1_oai222_4x ( z, c1, c2, b1, b2, a1, a2 ); output z; input c1; input c2; input b1; input b2; input a1; input a2; assign z = ~(( c1 | c2 ) & ( a1|a2 ) & (b1|b2)); endmodule //bw_u1_oai311_1x // // module bw_u1_oai311_1x ( z, c1, c2, c3, b, a ); output z; input c1; input c2; input c3; input b; input a; assign z = ~(( c1 | c2|c3 ) & ( a ) & (b)); endmodule //bw_u1_oai311_2x // // module bw_u1_oai311_2x ( z, c1, c2, c3, b, a ); output z; input c1; input c2; input c3; input b; input a; assign z = ~(( c1 | c2|c3 ) & ( a ) & (b)); endmodule //bw_u1_oai311_4x // // module bw_u1_oai311_4x ( z, c1, c2, c3, b, a ); output z; input c1; input c2; input c3; input b; input a; assign z = ~(( c1 | c2 | c3 ) & ( a ) & (b)); endmodule //bw_u1_oai311_8x // // module bw_u1_oai311_8x ( z, c1, c2, c3, b, a ); output z; input c1; input c2; input c3; input b; input a; assign z = ~(( c1 | c2|c3 ) & ( a ) & (b)); endmodule //bw_u1_muxi21_0p6x module bw_u1_muxi21_0p6x (z, d0, d1, s); output z; input d0, d1, s; assign z = s ? ~d1 : ~d0; endmodule //bw_u1_muxi21_1x module bw_u1_muxi21_1x (z, d0, d1, s); output z; input d0, d1, s; assign z = s ? ~d1 : ~d0; endmodule `endif //bw_u1_muxi21_2x module bw_u1_muxi21_2x (z, d0, d1, s); output z; input d0, d1, s; assign z = s ? ~d1 : ~d0; endmodule `ifndef SIMPLY_RISC_TWEAKS //bw_u1_muxi21_4x module bw_u1_muxi21_4x (z, d0, d1, s); output z; input d0, d1, s; assign z = s ? ~d1 : ~d0; endmodule `endif //bw_u1_muxi21_6x module bw_u1_muxi21_6x (z, d0, d1, s); output z; input d0, d1, s; assign z = s ? ~d1 : ~d0; endmodule `ifndef SIMPLY_RISC_TWEAKS //bw_u1_muxi31d_4x // module bw_u1_muxi31d_4x (z, d0, d1, d2, s0, s1, s2); output z; input d0, d1, d2, s0, s1, s2; zmuxi31d_prim i0 ( z, d0, d1, d2, s0, s1, s2 ); endmodule //bw_u1_muxi41d_4x // module bw_u1_muxi41d_4x (z, d0, d1, d2, d3, s0, s1, s2, s3); output z; input d0, d1, d2, d3, s0, s1, s2, s3; zmuxi41d_prim i0 ( z, d0, d1, d2, d3, s0, s1, s2, s3 ); endmodule //bw_u1_muxi41d_6x // module bw_u1_muxi41d_6x (z, d0, d1, d2, d3, s0, s1, s2, s3); output z; input d0, d1, d2, d3, s0, s1, s2, s3; zmuxi41d_prim i0 ( z, d0, d1, d2, d3, s0, s1, s2, s3 ); endmodule //bw_u1_xor2_0p6x // // module bw_u1_xor2_0p6x ( z, a, b ); output z; input a; input b; assign z = ( a ^ b ); endmodule //bw_u1_xor2_1x // // module bw_u1_xor2_1x ( z, a, b ); output z; input a; input b; assign z = ( a ^ b ); endmodule //bw_u1_xor2_2x // // module bw_u1_xor2_2x ( z, a, b ); output z; input a; input b; assign z = ( a ^ b ); endmodule //bw_u1_xor2_4x // // module bw_u1_xor2_4x ( z, a, b ); output z; input a; input b; assign z = ( a ^ b ); endmodule //bw_u1_xnor2_0p6x // // module bw_u1_xnor2_0p6x ( z, a, b ); output z; input a; input b; assign z = ~( a ^ b ); endmodule //bw_u1_xnor2_1x // // module bw_u1_xnor2_1x ( z, a, b ); output z; input a; input b; assign z = ~( a ^ b ); endmodule //bw_u1_xnor2_2x // // module bw_u1_xnor2_2x ( z, a, b ); output z; input a; input b; assign z = ~( a ^ b ); endmodule //bw_u1_xnor2_4x // // module bw_u1_xnor2_4x ( z, a, b ); output z; input a; input b; assign z = ~( a ^ b ); endmodule `endif //bw_u1_buf_1x // module bw_u1_buf_1x ( z, a ); output z; input a; assign z = ( a ); endmodule //bw_u1_buf_5x // module bw_u1_buf_5x ( z, a ); output z; input a; assign z = ( a ); endmodule //bw_u1_buf_10x // module bw_u1_buf_10x ( z, a ); output z; input a; assign z = ( a ); endmodule `ifndef SIMPLY_RISC_TWEAKS //bw_u1_buf_15x // module bw_u1_buf_15x ( z, a ); output z; input a; assign z = ( a ); endmodule `endif //bw_u1_buf_20x // module bw_u1_buf_20x ( z, a ); output z; input a; assign z = ( a ); endmodule //bw_u1_buf_30x // module bw_u1_buf_30x ( z, a ); output z; input a; assign z = ( a ); endmodule `ifndef SIMPLY_RISC_TWEAKS //bw_u1_buf_40x // module bw_u1_buf_40x ( z, a ); output z; input a; assign z = ( a ); endmodule //bw_u1_ao2222_1x // // module bw_u1_ao2222_1x ( z, a1, a2, b1, b2, c1, c2, d1, d2 ); output z; input a1; input a2; input b1; input b2; input c1; input c2; input d1; input d2; assign z = ((d1&d2) | ( c1 & c2 ) | (b1&b2)| (a1& a2)); endmodule //bw_u1_ao2222_2x // // module bw_u1_ao2222_2x ( z, a1, a2, b1, b2, c1, c2, d1, d2 ); output z; input a1; input a2; input b1; input b2; input c1; input c2; input d1; input d2; assign z = ((d1&d2) | ( c1 & c2 ) | (b1&b2)| (a1& a2)); endmodule //bw_u1_ao2222_4x // // module bw_u1_ao2222_4x ( z, a1, a2, b1, b2, c1, c2, d1, d2 ); output z; input a1; input a2; input b1; input b2; input c1; input c2; input d1; input d2; assign z = ((d1&d2) | ( c1 & c2 ) | (b1&b2)| (a1& a2)); endmodule //////////////////////////////////////////////////////////////////////// // // flipflops { // //////////////////////////////////////////////////////////////////////// // scanable D-flipflop with scanout module bw_u1_soff_1x (q, so, ck, d, se, sd); output q, so; input ck, d, se, sd; zsoff_prim i0 ( q, so, ck, d, se, sd ); endmodule module bw_u1_soff_2x (q, so, ck, d, se, sd); output q, so; input ck, d, se, sd; zsoff_prim i0 ( q, so, ck, d, se, sd ); endmodule module bw_u1_soff_4x (q, so, ck, d, se, sd); output q, so; input ck, d, se, sd; zsoff_prim i0 ( q, so, ck, d, se, sd ); endmodule module bw_u1_soff_8x (q, so, ck, d, se, sd); output q, so; input ck, d, se, sd; zsoff_prim i0 ( q, so, ck, d, se, sd ); endmodule // fast scanable D-flipflop with scanout with inverted Q output module bw_u1_soffi_4x (q_l, so, ck, d, se, sd); output q_l, so; input ck, d, se, sd; zsoffi_prim i0 ( q_l, so, ck, d, se, sd ); endmodule module bw_u1_soffi_8x (q_l, so, ck, d, se, sd); output q_l, so; input ck, d, se, sd; zsoffi_prim i0 ( q_l, so, ck, d, se, sd ); endmodule `endif // scanable D-flipflop with scanout with 2-to-1 input mux module bw_u1_soffm2_4x (q, so, ck, d0, d1, s, se, sd); output q, so; input ck, d0, d1, s, se, sd; zsoffm2_prim i0 ( q, so, ck, d0, d1, s, se, sd ); endmodule `ifndef SIMPLY_RISC_TWEAKS module bw_u1_soffm2_8x (q, so, ck, d0, d1, s, se, sd); output q, so; input ck, d0, d1, s, se, sd; zsoffm2_prim i0 ( q, so, ck, d0, d1, s, se, sd ); endmodule // scanable D-flipflop with scanout with sync reset-bar module bw_u1_soffr_2x (q, so, ck, d, se, sd, r_l); output q, so; input ck, d, se, sd, r_l; zsoffr_prim i0 ( q, so, ck, d, se, sd, r_l ); endmodule module bw_u1_soffr_4x (q, so, ck, d, se, sd, r_l); output q, so; input ck, d, se, sd, r_l; zsoffr_prim i0 ( q, so, ck, d, se, sd, r_l ); endmodule module bw_u1_soffr_8x (q, so, ck, d, se, sd, r_l); output q, so; input ck, d, se, sd, r_l; zsoffr_prim i0 ( q, so, ck, d, se, sd, r_l ); endmodule //bw_u1_soffasr_2x module bw_u1_soffasr_2x (q, so, ck, d, r_l, s_l, se, sd); output q, so; input ck, d, r_l, s_l, se, sd; zsoffasr_prim i0 (q, so, ck, d, r_l, s_l, se, sd); endmodule //bw_u1_ckbuf_1p5x module bw_u1_ckbuf_1p5x (clk, rclk); output clk; input rclk; buf (clk, rclk); endmodule //bw_u1_ckbuf_3x module bw_u1_ckbuf_3x (clk, rclk); output clk; input rclk; buf (clk, rclk); endmodule //bw_u1_ckbuf_4p5x module bw_u1_ckbuf_4p5x (clk, rclk); output clk; input rclk; buf (clk, rclk); endmodule //bw_u1_ckbuf_6x module bw_u1_ckbuf_6x (clk, rclk); output clk; input rclk; buf (clk, rclk); endmodule //bw_u1_ckbuf_7x // module bw_u1_ckbuf_7x (clk, rclk); output clk; input rclk; buf (clk, rclk); endmodule //bw_u1_ckbuf_8x // module bw_u1_ckbuf_8x (clk, rclk); output clk; input rclk; buf (clk, rclk); endmodule //bw_u1_ckbuf_11x // module bw_u1_ckbuf_11x (clk, rclk); output clk; input rclk; assign clk = ( rclk ); endmodule //bw_u1_ckbuf_14x // module bw_u1_ckbuf_14x (clk, rclk); output clk; input rclk; assign clk = ( rclk ); endmodule //bw_u1_ckbuf_17x // module bw_u1_ckbuf_17x (clk, rclk); output clk; input rclk; assign clk = ( rclk ); endmodule //bw_u1_ckbuf_19x // module bw_u1_ckbuf_19x (clk, rclk); output clk; input rclk; assign clk = ( rclk ); endmodule //bw_u1_ckbuf_22x // module bw_u1_ckbuf_22x (clk, rclk); output clk; input rclk; assign clk = ( rclk ); endmodule //bw_u1_ckbuf_25x // module bw_u1_ckbuf_25x (clk, rclk); output clk; input rclk; assign clk = ( rclk ); endmodule //bw_u1_ckbuf_28x // module bw_u1_ckbuf_28x (clk, rclk); output clk; input rclk; assign clk = ( rclk ); endmodule //bw_u1_ckbuf_30x // module bw_u1_ckbuf_30x (clk, rclk); output clk; input rclk; assign clk = ( rclk ); endmodule //bw_u1_ckbuf_33x // module bw_u1_ckbuf_33x (clk, rclk); output clk; input rclk; assign clk = ( rclk ); endmodule //bw_u1_ckbuf_40x // module bw_u1_ckbuf_40x (clk, rclk); output clk; input rclk; assign clk = ( rclk ); endmodule // gated clock buffers module bw_u1_ckenbuf_6x (clk, rclk, en_l, tm_l); output clk; input rclk, en_l, tm_l; zckenbuf_prim i0 ( clk, rclk, en_l, tm_l ); endmodule module bw_u1_ckenbuf_14x (clk, rclk, en_l, tm_l); output clk; input rclk, en_l, tm_l; zckenbuf_prim i0 ( clk, rclk, en_l, tm_l ); endmodule //////////////////////////////////////////////////////////////////////// // // half cells // //////////////////////////////////////////////////////////////////////// module bw_u1_zhinv_0p6x (z, a); output z; input a; not (z, a); endmodule module bw_u1_zhinv_1x (z, a); output z; input a; not (z, a); endmodule module bw_u1_zhinv_1p4x (z, a); output z; input a; not (z, a); endmodule module bw_u1_zhinv_2x (z, a); output z; input a; not (z, a); endmodule module bw_u1_zhinv_3x (z, a); output z; input a; not (z, a); endmodule module bw_u1_zhinv_4x (z, a); output z; input a; not (z, a); endmodule module bw_u1_zhnand2_0p4x (z, a, b); output z; input a, b; nand (z, a, b); endmodule module bw_u1_zhnand2_0p6x (z, a, b); output z; input a, b; nand (z, a, b); endmodule module bw_u1_zhnand2_1x (z, a, b); output z; input a, b; nand (z, a, b); endmodule module bw_u1_zhnand2_1p4x (z, a, b); output z; input a, b; nand (z, a, b); endmodule module bw_u1_zhnand2_2x (z, a, b); output z; input a, b; nand (z, a, b); endmodule module bw_u1_zhnand2_3x (z, a, b); output z; input a, b; nand (z, a, b); endmodule module bw_u1_zhnand3_0p6x (z, a, b, c); output z; input a, b, c; nand (z, a, b, c); endmodule module bw_u1_zhnand3_1x (z, a, b, c); output z; input a, b, c; nand (z, a, b, c); endmodule module bw_u1_zhnand3_2x (z, a, b, c); output z; input a, b, c; nand (z, a, b, c); endmodule module bw_u1_zhnand4_0p6x (z, a, b, c, d); output z; input a, b, c, d; nand (z, a, b, c, d); endmodule module bw_u1_zhnand4_1x (z, a, b, c, d); output z; input a, b, c, d; nand (z, a, b, c, d); endmodule module bw_u1_zhnand4_2x (z, a, b, c, d); output z; input a, b, c, d; nand (z, a, b, c, d); endmodule module bw_u1_zhnor2_0p6x (z, a, b); output z; input a, b; nor (z, a, b); endmodule module bw_u1_zhnor2_1x (z, a, b); output z; input a, b; nor (z, a, b); endmodule module bw_u1_zhnor2_2x (z, a, b); output z; input a, b; nor (z, a, b); endmodule module bw_u1_zhnor3_0p6x (z, a, b, c); output z; input a, b, c; nor (z, a, b, c); endmodule module bw_u1_zhaoi21_0p4x (z,b1,b2,a); output z; input b1; input b2; input a; assign z = ~(( b1 & b2 ) | ( a )); endmodule module bw_u1_zhaoi21_1x (z, a, b1, b2); output z; input b1; input b2; input a; assign z = ~(( b1 & b2 ) | ( a )); endmodule module bw_u1_zhoai21_1x (z,b1,b2,a ); output z; input b1; input b2; input a; assign z = ~(( b1 | b2 ) & ( a )); endmodule module bw_u1_zhoai211_0p3x (z, a, b, c1, c2); output z; input c1; input c2; input b; input a; assign z = ~(( c1 | c2 ) & ( a ) & (b)); endmodule module bw_u1_zhoai211_1x (z, a, b, c1, c2); output z; input a, b, c1, c2; assign z = ~(( c1 | c2 ) & ( a ) & (b)); endmodule /////////////// Scan data lock up latch /////////////// module bw_u1_scanlg_2x (so, sd, ck, se); output so; input sd, ck, se; reg so_l; assign so = ~so_l; always @ ( ck or sd or se ) if (~ck) so_l <= ~(sd & se) ; endmodule module bw_u1_scanl_2x (so, sd, ck); output so; input sd, ck; reg so_l; assign so = ~so_l; always @ ( ck or sd ) if (~ck) so_l <= ~sd ; endmodule ////////////////// Synchronizer //////////////// module bw_u1_syncff_4x (q, so, ck, d, se, sd); output q, so; input ck, d, se, sd; reg q_r; always @ (posedge ck) q_r <= se ? sd : d; assign q = q_r; assign so = q_r; endmodule //////////////////////////////////////////////////////////////////////// // // non library cells // //////////////////////////////////////////////////////////////////////// // These cells are used only in custom DP macros // Do not use in any block design without prior permission module bw_u1_zzeccxor2_5x (z, a, b); output z; input a, b; assign z = ( a ^ b ); endmodule module bw_u1_zzmulcsa42_5x (sum, carry, cout, a, b, c, d, cin); output sum, carry, cout; input a, b, c, d, cin; wire and_cin_b, or_cin_b, xor_a_c_d, and_or_cin_b_xor_a_c_d; wire and_a_c, and_a_d, and_c_d; assign sum = cin ^ a ^ b ^ c ^ d; assign carry = cin & b | (cin | b) & (a ^ c ^ d); assign cout = a & c | a & d | c & d; endmodule module bw_u1_zzmulcsa32_5x (sum, cout, a, b, c); output sum, cout; input a, b, c; wire and_a_b, and_a_c, and_b_c; assign sum = a ^ b ^ c ; assign cout = a & b | a & c | b & c ; endmodule module bw_u1_zzmulppmuxi21_2x ( z, d0, d1, s ); output z; input d0, d1, s; assign z = s ? ~d1 : ~d0; endmodule module bw_u1_zzmulnand2_2x ( z, a, b ); output z; input a; input b; assign z = ~( a & b ); endmodule // Primitives module zmuxi31d_prim (z, d0, d1, d2, s0, s1, s2); output z; input d0, d1, d2, s0, s1, s2; // for Blacktie `ifdef VERPLEX $constraint dp_1h3 ($one_hot ({s0,s1,s2})); `endif wire [2:0] sel = {s0,s1,s2}; // 0in one_hot reg z; always @ (s2 or d2 or s1 or d1 or s0 or d0) casez ({s2,d2,s1,d1,s0,d0}) 6'b0?0?10: z = 1'b1; 6'b0?0?11: z = 1'b0; 6'b0?100?: z = 1'b1; 6'b0?110?: z = 1'b0; 6'b0?1010: z = 1'b1; 6'b0?1111: z = 1'b0; 6'b100?0?: z = 1'b1; 6'b110?0?: z = 1'b0; 6'b100?10: z = 1'b1; 6'b110?11: z = 1'b0; 6'b10100?: z = 1'b1; 6'b11110?: z = 1'b0; 6'b101010: z = 1'b1; 6'b111111: z = 1'b0; default: z = 1'bx; endcase endmodule module zmuxi41d_prim (z, d0, d1, d2, d3, s0, s1, s2, s3); output z; input d0, d1, d2, d3, s0, s1, s2, s3; // for Blacktie `ifdef VERPLEX $constraint dp_1h4 ($one_hot ({s0,s1,s2,s3})); `endif wire [3:0] sel = {s0,s1,s2,s3}; // 0in one_hot reg z; always @ (s3 or d3 or s2 or d2 or s1 or d1 or s0 or d0) casez ({s3,d3,s2,d2,s1,d1,s0,d0}) 8'b0?0?0?10: z = 1'b1; 8'b0?0?0?11: z = 1'b0; 8'b0?0?100?: z = 1'b1; 8'b0?0?110?: z = 1'b0; 8'b0?0?1010: z = 1'b1; 8'b0?0?1111: z = 1'b0; 8'b0?100?0?: z = 1'b1; 8'b0?110?0?: z = 1'b0; 8'b0?100?10: z = 1'b1; 8'b0?110?11: z = 1'b0; 8'b0?10100?: z = 1'b1; 8'b0?11110?: z = 1'b0; 8'b0?101010: z = 1'b1; 8'b0?111111: z = 1'b0; 8'b100?0?0?: z = 1'b1; 8'b110?0?0?: z = 1'b0; 8'b100?0?10: z = 1'b1; 8'b110?0?11: z = 1'b0; 8'b100?100?: z = 1'b1; 8'b110?110?: z = 1'b0; 8'b100?1010: z = 1'b1; 8'b110?1111: z = 1'b0; 8'b10100?0?: z = 1'b1; 8'b11110?0?: z = 1'b0; 8'b10100?10: z = 1'b1; 8'b11110?11: z = 1'b0; 8'b1010100?: z = 1'b1; 8'b1111110?: z = 1'b0; 8'b10101010: z = 1'b1; 8'b11111111: z = 1'b0; default: z = 1'bx; endcase endmodule module zsoff_prim (q, so, ck, d, se, sd); output q, so; input ck, d, se, sd; reg q_r; always @ (posedge ck) q_r <= se ? sd : d; assign q = q_r; assign so = q_r ; endmodule module zsoffr_prim (q, so, ck, d, se, sd, r_l); output q, so; input ck, d, se, sd, r_l; reg q_r; always @ (posedge ck) q_r <= se ? sd : (d & r_l) ; assign q = q_r; assign so = q_r; endmodule module zsoffi_prim (q_l, so, ck, d, se, sd); output q_l, so; input ck, d, se, sd; reg q_r; always @ (posedge ck) q_r <= se ? sd : d; assign q_l = ~q_r; assign so = q_r; endmodule `endif module zsoffm2_prim (q, so, ck, d0, d1, s, se, sd); output q, so; input ck, d0, d1, s, se, sd; reg q_r; always @ (posedge ck) q_r <= se ? sd : (s ? d1 : d0) ; assign q = q_r; assign so = q_r; endmodule `ifndef SIMPLY_RISC_TWEAKS module zsoffasr_prim (q, so, ck, d, r_l, s_l, se, sd); output q, so; input ck, d, r_l, s_l, se, sd; // asynchronous reset and asynchronous set // (priority: r_l > s_l > se > d) reg q; wire so; always @ (posedge ck or negedge r_l or negedge s_l) begin if(~r_l) q <= 1'b0; else if (~s_l) q <= r_l; else if (se) q <= r_l & s_l & sd; else q <= r_l & s_l & (~se) & d; end assign so = q | ~se; endmodule module zckenbuf_prim (clk, rclk, en_l, tm_l); output clk; input rclk, en_l, tm_l; reg clken; always @ (rclk or en_l or tm_l) if (!rclk) //latch opens on rclk low phase clken <= ~en_l | ~tm_l; assign clk = clken & rclk; endmodule module bw_mckbuf_40x (clk, rclk, en); output clk; input rclk; input en; assign clk = rclk & en ; endmodule module bw_mckbuf_33x (clk, rclk, en); output clk; input rclk; input en; assign clk = rclk & en ; endmodule module bw_mckbuf_30x (clk, rclk, en); output clk; input rclk; input en; assign clk = rclk & en ; endmodule module bw_mckbuf_28x (clk, rclk, en); output clk; input rclk; input en; assign clk = rclk & en ; endmodule module bw_mckbuf_25x (clk, rclk, en); output clk; input rclk; input en; assign clk = rclk & en ; endmodule module bw_mckbuf_22x (clk, rclk, en); output clk; input rclk; input en; assign clk = rclk & en ; endmodule module bw_mckbuf_19x (clk, rclk, en); output clk; input rclk; input en; assign clk = rclk & en ; endmodule module bw_mckbuf_17x (clk, rclk, en); output clk; input rclk; input en; assign clk = rclk & en ; endmodule module bw_mckbuf_14x (clk, rclk, en); output clk; input rclk; input en; assign clk = rclk & en ; endmodule module bw_mckbuf_11x (clk, rclk, en); output clk; input rclk; input en; assign clk = rclk & en ; endmodule module bw_mckbuf_8x (clk, rclk, en); output clk; input rclk; input en; assign clk = rclk & en ; endmodule module bw_mckbuf_7x (clk, rclk, en); output clk; input rclk; input en; assign clk = rclk & en ; endmodule module bw_mckbuf_6x (clk, rclk, en); output clk; input rclk; input en; assign clk = rclk & en ; endmodule module bw_mckbuf_4p5x (clk, rclk, en); output clk; input rclk; input en; assign clk = rclk & en ; endmodule module bw_mckbuf_3x (clk, rclk, en); output clk; input rclk; input en; assign clk = rclk & en ; endmodule module bw_mckbuf_1p5x (clk, rclk, en); output clk; input rclk; input en; assign clk = rclk & en ; endmodule //bw_u1_minbuf_1x // module bw_u1_minbuf_1x ( z, a ); output z; input a; assign z = ( a ); endmodule //bw_u1_minbuf_4x // module bw_u1_minbuf_4x ( z, a ); output z; input a; assign z = ( a ); endmodule `endif //bw_u1_minbuf_5x // module bw_u1_minbuf_5x ( z, a ); output z; input a; assign z = ( a ); endmodule `ifndef SIMPLY_RISC_TWEAKS module bw_u1_ckenbuf_4p5x (clk, rclk, en_l, tm_l); output clk; input rclk, en_l, tm_l; zckenbuf_prim i0 ( clk, rclk, en_l, tm_l ); endmodule // dummy fill modules to get rid of DFT "CAP" property errors (bug 5487) module bw_u1_fill_1x(\vdd! ); input \vdd! ; endmodule module bw_u1_fill_2x(\vdd! ); input \vdd! ; endmodule module bw_u1_fill_3x(\vdd! ); input \vdd! ; endmodule module bw_u1_fill_4x(\vdd! ); input \vdd! ; endmodule `endif