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https://opencores.org/ocsvn/s1_core/s1_core/trunk
Subversion Repositories s1_core
[/] [s1_core/] [trunk/] [tools/] [bin/] [s1_synth] - Rev 111
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#!/bin/bash
set -e
if ( (test $# != 1) || ((test $1 != "xst") && (test $1 != "fpga") && (test $1 != "dc")) ) then
echo "Usage: $0 {xst|fpga|dc}"
exit 1
fi
test_var S1_ROOT
echo -e "Synthesizing the design using $1"
mkdir -p $S1_ROOT/run/synth/$1
cd $S1_ROOT/run/synth/$1
rm -rf * .syn*
if(test $1 == "xst") then
xst -ifn $S1_ROOT/tools/src/build_xst.cmd -ofn synth.log
#export TOP_LEVEL="s1_top"
#ngdbuild ${TOP_LEVEL}
#map -o ${TOP_LEVEL}_map.ncd ${TOP_LEVEL}
#par -w -ol high ${TOP_LEVEL}_map.ncd ${TOP_LEVEL}.ncd
#bitgen -g startupclk:Cclk -w ${TOP_LEVEL} ${TOP_LEVEL}.bit
#trce ${TOP_LEVEL} ${TOP_LEVEL}_map
fi
if(test $1 == "fpga") then
iverilog -g1 -t xnf -o fpga.edif -c$FILELIST_FPGA 2>&1 | tee synth.log
fi
if(test $1 == "dc") then
mkdir work
ln -s -f ../../../tools/src/synopsys_dc.setup .synopsys_dc.setup
dc_shell -tcl_mode -f $FILELIST_DC 2>&1 | tee synth.log
fi
echo -e "Synthesis with $1 done!"