Subversion Repositories s1_core

#!/bin/bash

test_var S1_ROOT

# Create the Icarus filelist (for Icarus simulation)
rm -f $FILELIST_ICARUS
touch $FILELIST_ICARUS
find $S1_ROOT/hdl/behav/sparc_libs -name "*.v" >> $FILELIST_ICARUS
find $S1_ROOT/hdl/rtl/sparc_core -name "*.v" >> $FILELIST_ICARUS
echo $S1_ROOT/hdl/rtl/s1_top/rst_ctrl.v >> $FILELIST_ICARUS
echo $S1_ROOT/hdl/rtl/s1_top/int_ctrl.v >> $FILELIST_ICARUS
echo $S1_ROOT/hdl/rtl/s1_top/spc2wbm.v >> $FILELIST_ICARUS
echo $S1_ROOT/hdl/rtl/s1_top/s1_top.v >> $FILELIST_ICARUS
echo $S1_ROOT/hdl/behav/testbench/mem_harness.v >> $FILELIST_ICARUS
echo $S1_ROOT/hdl/behav/testbench/testbench.v >> $FILELIST_ICARUS
# echo "+incdir+"`find $S1_ROOT/hdl/rtl/sparc_core -name "include"` >> $FILELIST_ICARUS
echo "+incdir+"$S1_ROOT/hdl/rtl/s1_top >> $FILELIST_ICARUS
echo "+define+FPGA_SYN" >> $FILELIST_ICARUS
echo "+define+FPGA_SYN_1THREAD" >> $FILELIST_ICARUS
echo "+define+FPGA_SYN_NO_SPU" >> $FILELIST_ICARUS
echo "+define+DEBUG" >> $FILELIST_ICARUS

# Create the VCS filelist (for Synopsys simulation)
rm -f $FILELIST_VCS
touch $FILELIST_VCS
find $S1_ROOT/hdl/behav/sparc_libs -name "*.v" >> $FILELIST_VCS
find $S1_ROOT/hdl/rtl/sparc_core -name "*.v" >> $FILELIST_VCS
sed -e 's/^/\-v /g' $FILELIST_VCS > temp.v
mv -f temp.v $FILELIST_VCS
echo $S1_ROOT/hdl/rtl/s1_top/rst_ctrl.v >> $FILELIST_VCS
echo $S1_ROOT/hdl/rtl/s1_top/int_ctrl.v >> $FILELIST_VCS
echo $S1_ROOT/hdl/rtl/s1_top/spc2wbm.v >> $FILELIST_VCS
echo $S1_ROOT/hdl/rtl/s1_top/s1_top.v >> $FILELIST_VCS
echo $S1_ROOT/hdl/behav/testbench/mem_harness.v >> $FILELIST_VCS
echo $S1_ROOT/hdl/behav/testbench/testbench.v >> $FILELIST_VCS
# echo "+incdir+"`find $S1_ROOT/hdl/rtl/sparc_core -name "include"` >> $FILELIST_VCS
echo "+incdir+"$S1_ROOT/hdl/rtl/s1_top >> $FILELIST_VCS
## TODO
# please find the proper option for the defines and put them here!!!

# Create the FPGA filelist (for Icarus synthesis)
rm -f $FILELIST_FPGA
touch $FILELIST_FPGA
find $S1_ROOT/hdl/behav/sparc_libs -name "*.v" >> $FILELIST_FPGA
find $S1_ROOT/hdl/rtl/sparc_core -name "*.v" >> $FILELIST_FPGA
echo $S1_ROOT/hdl/rtl/s1_top/rst_ctrl.v >> $FILELIST_FPGA
echo $S1_ROOT/hdl/rtl/s1_top/int_ctrl.v >> $FILELIST_FPGA
echo $S1_ROOT/hdl/rtl/s1_top/spc2wbm.v >> $FILELIST_FPGA
echo $S1_ROOT/hdl/rtl/s1_top/s1_top.v >> $FILELIST_FPGA
# echo "+incdir+"`find $S1_ROOT/hdl/rtl/sparc_core -name "include"` >> $FILELIST_FPGA
echo "+incdir+"$S1_ROOT/hdl/rtl/s1_top >> $FILELIST_FPGA
echo "+define+FPGA_SYN" >> $FILELIST_FPGA
echo "+define+FPGA_SYN_1THREAD" >> $FILELIST_FPGA
echo "+define+FPGA_SYN_NO_SPU" >> $FILELIST_FPGA

# Create the DC filelist (for Synopsys synthesis)
rm -f $FILELIST_DC
touch $FILELIST_DC
find $S1_ROOT/hdl/behav/sparc_libs -name "*.v" >> $FILELIST_DC
find $S1_ROOT/hdl/rtl/sparc_core -name "*.v" >> $FILELIST_DC
echo $S1_ROOT/hdl/rtl/s1_top/rst_ctrl.v >> $FILELIST_DC
echo $S1_ROOT/hdl/rtl/s1_top/int_ctrl.v >> $FILELIST_DC
echo $S1_ROOT/hdl/rtl/s1_top/spc2wbm.v >> $FILELIST_DC
echo $S1_ROOT/hdl/rtl/s1_top/s1_top.v >> $FILELIST_DC
sed -e 's/^/analyze \-format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /g' $FILELIST_DC > temp.v
mv -f temp.v $FILELIST_DC
cat $S1_ROOT/tools/src/build_dc.cmd >> $FILELIST_DC

# Create the XST filelist (for Xilinx ISE synthesis)
rm -f $FILELIST_XST
touch $FILELIST_XST
find $S1_ROOT/hdl/behav/sparc_libs -name "*.v" >> $FILELIST_XST
find $S1_ROOT/hdl/rtl/sparc_core -name "*.v" >> $FILELIST_XST
echo $S1_ROOT/hdl/rtl/s1_top/rst_ctrl.v >> $FILELIST_XST
echo $S1_ROOT/hdl/rtl/s1_top/int_ctrl.v >> $FILELIST_XST
echo $S1_ROOT/hdl/rtl/s1_top/spc2wbm.v >> $FILELIST_XST
echo $S1_ROOT/hdl/rtl/s1_top/s1_top.v >> $FILELIST_XST
sed -e 's/^/verilog work /g' $FILELIST_XST > temp.v
mv -f temp.v $FILELIST_XST