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[/] [s6soc/] [trunk/] [rtl/] [Makefile] - Rev 13
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################################################################################
#
# Filename: rtl/Makefile
#
# Project: CMod S6 System on a Chip, ZipCPU demonstration project
#
# Purpose: This makefile builds a verilator simulation of the zipsystem.
# It does not make the system within Vivado or Quartus.
#
# Creator: Dan Gisselquist, Ph.D.
# Gisselquist Technology, LLC
#
################################################################################
#
# Copyright (C) 2015-2016, Gisselquist Technology, LLC
#
# This program is free software (firmware): you can redistribute it and/or
# modify it under the terms of the GNU General Public License as published
# by the Free Software Foundation, either version 3 of the License, or (at
# your option) any later version.
#
# This program is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for more details.
#
# You should have received a copy of the GNU General Public License along
# with this program. (It's in the $(ROOT)/doc directory, run make with no
# target there if the PDF file isn't present.) If not, see
# <http://www.gnu.org/licenses/> for a copy.
#
# License: GPL, v3, as defined and found on www.gnu.org,
# http://www.gnu.org/licenses/gpl.html
#
#
################################################################################
#
#
.PHONY: all
all: busmaster altbusmaster
CPUD := cpu
RAWZIP := zipbones.v zipcpu.v cpudefs.v \
prefetch.v idecode.v cpuops.v memops.v \
wbdblpriarb.v
ZIPSRC := $(addprefix $(CPUD)/,$(RAWZIP))
BUSSRC := builddate.v llqspi.v wbicape6.v wbicapesimple.v wbscope.v \
memdev.v rtclight.v spio.v wbgpio.v wbpwmaudio.v
MAINSRC := busmaster.v builddate.v flash_config.v wbqspiflash.v \
$(BUSSRC) $(ZIPSRC)
# toplevel.v rxuart.v txuart.v
ALTSRC := altbusmaster.v builddate.v flash_config.v wbqspiflash.v \
$(BUSSRC) wbdeppsimple.v
# alttop.v rxuart.v txuart.v
# rtcdate.v wbubus.v
VOBJ := obj_dir
$(VOBJ)/Vbusmaster.cpp: $(MAINSRC)
verilator -cc -y $(CPUD) busmaster.v
$(VOBJ)/Vbusmaster.h: $(VOBJ)/Vbusmaster.cpp
$(VOBJ)/Valtbusmaster.cpp: $(ALTSRC)
verilator -cc -y $(CPUD) altbusmaster.v
$(VOBJ)/Valtbusmaster.h: $(VOBJ)/Valtbusmaster.cpp
$(VOBJ)/Vbusmaster__ALL.a: $(VOBJ)/Vbusmaster.cpp $(VOBJ)/Vbusmaster.h
cd $(VOBJ); make --no-print-directory -f Vbusmaster.mk
$(VOBJ)/Valtbusmaster__ALL.a: $(VOBJ)/Valtbusmaster.cpp $(VOBJ)/Valtbusmaster.h
cd $(VOBJ); make --no-print-directory -f Valtbusmaster.mk
cpudefs.h: cpudefs.v
@echo "Building cpudefs.h"
@echo "// " > $@
@echo "// Do not edit this file, it is automatically generated!" >> $@
@echo "// To generate this file, \"make cpudefs.h\" in the rtl directory." >> $@
@echo "// " >> $@
@grep "^\`" $^ | sed -e '{ s/^`/#/ }' >> $@
.PHONY: busmaster
busmaster: $(VOBJ)/Vbusmaster__ALL.a
.PHONY: altbusmaster
altbusmaster: $(VOBJ)/Valtbusmaster__ALL.a
.PHONY: clean
clean:
rm -rf $(VOBJ) cpudefs.h
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