OpenCores
URL https://opencores.org/ocsvn/sardmips/sardmips/trunk

Subversion Repositories sardmips

[/] [sardmips/] [branches/] [avendor/] [source/] [IGOR_A] - Rev 18

Compare with Previous | Blame | View Log

<?xml version="1.0"?>
<!-- GTKWave saved traces, version 2.0.0pre3-20030319 -->
<!-- at Tue Jan 24 18:36:08 2006 -->

<config>
 <decors>
  <decor name="default">
   <trace-state-colors>
    <named-color name="font" color="#00ff00"/>
    <named-color name="low" color="#00ff00"/>
    <named-color name="high" color="#00ff00"/>
    <named-color name="x" color="#00ff00"/>
    <named-color name="xfill" color="#008000"/>
    <named-color name="trans" color="#00ff00"/>
    <named-color name="mid" color="#00ff00"/>
    <named-color name="vtrans" color="#00ff00"/>
    <named-color name="vbox" color="#00ff00"/>
    <named-color name="unloaded" color="#800000"/>
    <named-color name="analog" color="#00ff00"/>
    <named-color name="clip" color="#ff0000"/>
   </trace-state-colors>
  </decor>
 </decors>

 <trace-groups>
  <trace-group name="default" decor="default">
  </trace-group>
 </trace-groups>

 <pane-colors>
  <named-color name="back" color="#181818"/>
  <named-color name="grid" color="#808080"/>
  <named-color name="mark" color="#0000ff"/>
  <named-color name="umark" color="#ffff00"/>
  <named-color name="pfont" color="#ffffff"/>
 </pane-colors>

 <markers>
  <marker name="primary" time="0 s"/>
 </markers>

 <traces>
  <trace name="SystemC.id_exception" mode="bin" rjustified="yes">
    <signal name="SystemC.id_exception"/>
  </trace>
  <trace name="SystemC.ex_exception" mode="bin" rjustified="yes">
    <signal name="SystemC.ex_exception"/>
  </trace>
  <trace name="SystemC.mem_exception" mode="bin" rjustified="yes">
    <signal name="SystemC.mem_exception"/>
  </trace>
  <trace name="SystemC.wb_exception" mode="bin" rjustified="yes">
    <signal name="SystemC.wb_exception"/>
  </trace>
  <trace name="SystemC.enable_pc" mode="bin" rjustified="yes">
    <signal name="SystemC.enable_pc"/>
  </trace>
  <trace name="SystemC.enable_fetch" mode="bin" rjustified="yes">
    <signal name="SystemC.enable_fetch"/>
  </trace>
  <trace name="SystemC.enable_decode" mode="bin" rjustified="yes">
    <signal name="SystemC.enable_decode"/>
  </trace>
  <trace name="SystemC.enable_execute" mode="bin" rjustified="yes">
    <signal name="SystemC.enable_execute"/>
  </trace>
  <trace name="SystemC.enable_memstage" mode="bin" rjustified="yes">
    <signal name="SystemC.enable_memstage"/>
  </trace>
  <trace name="SystemC.cause[31:0]" mode="hex" rjustified="yes">
    <signal name="SystemC.cause[31:0]"/>
  </trace>
  <trace name="SystemC.check_excep" mode="bin" rjustified="yes">
    <signal name="SystemC.check_excep"/>
  </trace>
  <trace name="SystemC.to_EPC[31:0]" mode="hex" rjustified="yes">
    <signal name="SystemC.to_EPC[31:0]"/>
  </trace>
  <trace name="SystemC.to_BadVAddr[31:0]" mode="hex" rjustified="yes">
    <signal name="SystemC.to_BadVAddr[31:0]"/>
  </trace>
  <trace name="SystemC.cp0_regs(8)[31:0]" mode="hex" rjustified="yes">
    <signal name="SystemC.cp0_regs(8)[31:0]"/>
  </trace>
  <trace name="SystemC.cp0_regs(12)[31:0]" mode="hex" rjustified="yes">
    <signal name="SystemC.cp0_regs(12)[31:0]"/>
  </trace>
  <trace name="SystemC.cp0_regs(13)[31:0]" mode="hex" rjustified="yes">
    <signal name="SystemC.cp0_regs(13)[31:0]"/>
  </trace>
  <trace name="SystemC.cp0_regs(14)[31:0]" mode="hex" rjustified="yes">
    <signal name="SystemC.cp0_regs(14)[31:0]"/>
  </trace>
  <trace name="SystemC.cpu.ex_mem_inst[31:0]" mode="hex" rjustified="yes">
    <signal name="SystemC.cpu.ex_mem_inst[31:0]"/>
  </trace>
  <trace name="SystemC.cpu.id_ex_inst[31:0]" mode="hex" rjustified="yes">
    <signal name="SystemC.cpu.id_ex_inst[31:0]"/>
  </trace>
  <trace name="SystemC.cpu.if_id_inst[31:0]" mode="hex" rjustified="yes">
    <signal name="SystemC.cpu.if_id_inst[31:0]"/>
  </trace>
  <trace name="SystemC.cpu.mem_wb_inst[31:0]" mode="hex" rjustified="yes">
    <signal name="SystemC.cpu.mem_wb_inst[31:0]"/>
  </trace>
  <trace name="SystemC.ex.id_ex_alu_function[5:0]" mode="hex" rjustified="yes">
    <signal name="SystemC.ex.id_ex_alu_function[5:0]"/>
  </trace>
  <trace name="SystemC.ex.id_ex_alu_opcode[5:0]" mode="hex" rjustified="yes">
    <signal name="SystemC.ex.id_ex_alu_opcode[5:0]"/>
  </trace>
  <trace name="SystemC.ex.stage0[63:0]" mode="hex" rjustified="yes">
    <signal name="SystemC.ex.stage0[63:0]"/>
  </trace>
  <trace name="SystemC.ex.lo[31:0]" mode="hex" rjustified="yes">
    <signal name="SystemC.ex.lo[31:0]"/>
  </trace>
  <trace name="SystemC.ex.hi[31:0]" mode="hex" rjustified="yes">
    <signal name="SystemC.ex.hi[31:0]"/>
  </trace>
  <trace name="SystemC.interrupt_signal" mode="bin" rjustified="yes">
    <signal name="SystemC.interrupt_signal"/>
  </trace>
  <trace name="SystemC.interrupt_signal_out" mode="bin" rjustified="yes">
    <signal name="SystemC.interrupt_signal_out"/>
  </trace>
 </traces>
</config>

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.