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https://opencores.org/ocsvn/sata_controller_core/sata_controller_core/trunk
Subversion Repositories sata_controller_core
[/] [sata_controller_core/] [trunk/] [sata2_bus_v1_00_a/] [README] - Rev 11
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This Xilinx Base System (created with 12.2) includes the SATA2 Core with
interfaces to PLB for command, control and status and to DDR through
NPI for data. A C test program which runs on Microblaze to exercise the core
is under "sata_test".
Note: Use Makefiles under the respective coregen directories of the SATA
and NPI cores to generate netlists for FIFOs and ILAs. Then copy or link
these to the netlist directories.