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https://opencores.org/ocsvn/sata_controller_core/sata_controller_core/trunk
Subversion Repositories sata_controller_core
[/] [sata_controller_core/] [trunk/] [sata2_bus_v1_00_a/] [base_system/] [__xps/] [system.xml] - Rev 11
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<EDKSYSTEM EDKVERSION="12.2" EDWVERSION="1.2" TIMESTAMP="Mon Jun 11 14:36:55 2012"><SYSTEMINFO ARCH="virtex6" DEVICE="xc6vlx240t" PACKAGE="ff1156" PART="xc6vlx240tff1156-1" SOURCE="/raid/home/aamendon/open_source/svn/sata_controller_core/sata_controller_core/trunk/sata2_bus_v1_00_a/base_system/" SPEEDGRADE="-1"/><EXTERNALPORTS><PORT DIR="I" MHS_INDEX="0" NAME="fpga_0_RS232_Uart_1_RX_pin" SIGNAME="fpga_0_RS232_Uart_1_RX_pin"/><PORT DIR="O" MHS_INDEX="1" NAME="fpga_0_RS232_Uart_1_TX_pin" SIGNAME="fpga_0_RS232_Uart_1_TX_pin"/><PORT DIR="O" MHS_INDEX="2" NAME="fpga_0_DDR3_SDRAM_DDR3_Clk_pin" SIGIS="CLK" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_Clk_pin"/><PORT DIR="O" MHS_INDEX="3" NAME="fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin" SIGIS="CLK" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin"/><PORT DIR="O" MHS_INDEX="4" NAME="fpga_0_DDR3_SDRAM_DDR3_CE_pin" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_CE_pin"/><PORT DIR="O" MHS_INDEX="5" NAME="fpga_0_DDR3_SDRAM_DDR3_CS_n_pin" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_CS_n_pin"/><PORT DIR="O" MHS_INDEX="6" NAME="fpga_0_DDR3_SDRAM_DDR3_ODT_pin" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_ODT_pin"/><PORT DIR="O" MHS_INDEX="7" NAME="fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin"/><PORT DIR="O" MHS_INDEX="8" NAME="fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin"/><PORT DIR="O" MHS_INDEX="9" NAME="fpga_0_DDR3_SDRAM_DDR3_WE_n_pin" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_WE_n_pin"/><PORT DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="10" MSB="2" NAME="fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin" RIGHT="0" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin"/><PORT DIR="O" ENDIAN="LITTLE" LEFT="12" LSB="0" MHS_INDEX="11" MSB="12" NAME="fpga_0_DDR3_SDRAM_DDR3_Addr_pin" RIGHT="0" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_Addr_pin"/><PORT DIR="IO" ENDIAN="LITTLE" LEFT="31" LSB="0" MHS_INDEX="12" MSB="31" NAME="fpga_0_DDR3_SDRAM_DDR3_DQ_pin" RIGHT="0" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_DQ_pin"/><PORT DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="13" MSB="3" NAME="fpga_0_DDR3_SDRAM_DDR3_DM_pin" RIGHT="0" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_DM_pin"/><PORT DIR="O" MHS_INDEX="14" NAME="fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin"/><PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="15" MSB="3" NAME="fpga_0_DDR3_SDRAM_DDR3_DQS_pin" RIGHT="0" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_DQS_pin"/><PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="16" MSB="3" NAME="fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin" RIGHT="0" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin"/><PORT CLKFREQUENCY="200000000" DIR="I" MHS_INDEX="17" NAME="fpga_0_clk_1_sys_clk_p_pin" SIGIS="CLK" SIGNAME="dcm_clk_s"/><PORT CLKFREQUENCY="200000000" DIR="I" MHS_INDEX="18" NAME="fpga_0_clk_1_sys_clk_n_pin" SIGIS="CLK" SIGNAME="dcm_clk_s"/><PORT DIR="I" MHS_INDEX="19" NAME="fpga_0_rst_1_sys_rst_pin" RSTPOLARITY="1" SIGIS="RST" SIGNAME="sys_rst_s"/><PORT DIR="O" MHS_INDEX="20" NAME="TILE0_PLLLKDET_OUT_N" SIGNAME="TILE0_PLLLKDET_OUT_N"/><PORT DIR="O" MHS_INDEX="21" NAME="DCMLOCKED_OUT" SIGNAME="DCMLOCKED_OUT"/><PORT DIR="O" MHS_INDEX="22" NAME="LINKUP_led" SIGNAME="LINKUP_led"/><PORT DIR="O" MHS_INDEX="23" NAME="GEN2_led" SIGNAME="GEN2_led"/><PORT DIR="O" MHS_INDEX="24" NAME="FMC_HPC_DP2_C2M_N" SIGNAME="TXN0_OUT"/><PORT DIR="O" MHS_INDEX="25" NAME="FMC_HPC_DP2_C2M_P" SIGNAME="TXP0_OUT"/><PORT DIR="I" MHS_INDEX="26" NAME="FMC_HPC_DP2_M2C_N" SIGNAME="RXN0_IN"/><PORT DIR="I" MHS_INDEX="27" NAME="FMC_HPC_DP2_M2C_P" SIGNAME="RXP0_IN"/></EXTERNALPORTS><MODULES><MODULE HWVERSION="1.00.a" INSTANCE="npi_core_0" IPTYPE="PERIPHERAL" MHS_INDEX="0" MODCLASS="PERIPHERAL" MODTYPE="npi_core"><DESCRIPTION TYPE="SHORT">NPI_CORE</DESCRIPTION><LICENSEINFO ICON_NAME="ps_core_local"/><PARAMETERS><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="CHIPSCOPE" TYPE="boolean" VALUE="true"/><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="1" NAME="RAM_OFFSET" TYPE="std_logic_vector" VALUE="0xd0"/><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="2" NAME="BLOCK_SIZE" TYPE="integer" VALUE="512"/></PARAMETERS><PORTS><PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="35" LSB="0" MHS_INDEX="0" MPD_INDEX="0" MSB="35" NAME="npi_if_ila_control" RIGHT="0" SIGNAME="npi_if_ila_control" VECFORMULA="[35:0]"/><PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="35" LSB="0" MHS_INDEX="1" MPD_INDEX="1" MSB="35" NAME="npi_if_tx_ila_control" RIGHT="0" SIGNAME="npi_if_tx_ila_control" VECFORMULA="[35:0]"/><PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="35" LSB="0" MHS_INDEX="2" MPD_INDEX="2" MSB="35" NAME="npi_ila_control" RIGHT="0" SIGNAME="npi_ila_control" VECFORMULA="[35:0]"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="3" MPD_INDEX="3" MSB="0" NAME="MPMC_Clk" RIGHT="0" SIGNAME="clk_200_0000MHzMMCM0"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="4" MPD_INDEX="4" MSB="0" NAME="user_clk" RIGHT="0" SIGNAME="SATA_CORE_CLK_OUT"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="5" MPD_INDEX="5" MSB="0" NAME="reset" RIGHT="0" SIGNAME="sys_rst_s"/><PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="6" MPD_INDEX="6" MSB="31" NAME="NPI_CORE_DIN" RIGHT="0" SIGNAME="SATA_CORE_DOUT" VECFORMULA="[31:0]"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="7" MPD_INDEX="7" MSB="0" NAME="NPI_CORE_WE" RIGHT="0" SIGNAME="SATA_CORE_DOUT_WE"/><PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="8" MPD_INDEX="9" MSB="31" NAME="NPI_CORE_DOUT" RIGHT="0" SIGNAME="SATA_CORE_DIN" VECFORMULA="[31:0]"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="9" MPD_INDEX="10" MSB="0" NAME="NPI_CORE_DOUT_WE" RIGHT="0" SIGNAME="SATA_CORE_DIN_WE"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="10" MPD_INDEX="11" MSB="0" NAME="SATA_CORE_FULL" RIGHT="0" SIGNAME="SATA_CORE_FULL"/><PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="11" MPD_INDEX="12" MSB="1" NAME="req_type" RIGHT="0" SIGNAME="NPI_CORE_REQ_TYPE" VECFORMULA="[1:0]"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="12" MPD_INDEX="13" MSB="0" NAME="new_cmd" RIGHT="0" SIGNAME="NPI_CORE_NEW_CMD"/><PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="13" MPD_INDEX="14" MSB="31" NAME="num_read_bytes_in" RIGHT="0" SIGNAME="NPI_CORE_NUM_RD_BYTES" VECFORMULA="[31:0]"/><PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="14" MPD_INDEX="15" MSB="31" NAME="num_write_bytes_in" RIGHT="0" SIGNAME="NPI_CORE_NUM_WR_BYTES" VECFORMULA="[31:0]"/><PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="15" MPD_INDEX="16" MSB="31" NAME="NPI_init_wr_addr_in" RIGHT="0" SIGNAME="NPI_CORE_INIT_WR_ADDR" VECFORMULA="[31:0]"/><PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="16" MPD_INDEX="17" MSB="31" NAME="NPI_init_rd_addr_in" RIGHT="0" SIGNAME="NPI_CORE_INIT_RD_ADDR" VECFORMULA="[31:0]"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="17" MPD_INDEX="18" MSB="0" NAME="NPI_ready_for_cmd" RIGHT="0" SIGNAME="NPI_CORE_READY_FOR_CMD"/><PORT DIR="O" MPD_INDEX="8" NAME="NPI_CORE_FULL" SIGNAME="__NOC__"/><PORT BUS="XIL_NPI" DEF_SIGNAME="npi_complete_0_XIL_NPI_Addr" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="NPI_Addr" RIGHT="0" SIGNAME="npi_complete_0_XIL_NPI_Addr" VECFORMULA="[31:0]"/><PORT BUS="XIL_NPI" DEF_SIGNAME="npi_complete_0_XIL_NPI_AddrReq" DIR="O" MPD_INDEX="20" NAME="NPI_AddrReq" SIGNAME="npi_complete_0_XIL_NPI_AddrReq"/><PORT BUS="XIL_NPI" DEF_SIGNAME="npi_complete_0_XIL_NPI_AddrAck" DIR="I" MPD_INDEX="21" NAME="NPI_AddrAck" SIGNAME="npi_complete_0_XIL_NPI_AddrAck"/><PORT BUS="XIL_NPI" DEF_SIGNAME="npi_complete_0_XIL_NPI_RNW" DIR="O" MPD_INDEX="22" NAME="NPI_RNW" SIGNAME="npi_complete_0_XIL_NPI_RNW"/><PORT BUS="XIL_NPI" DEF_SIGNAME="npi_complete_0_XIL_NPI_Size" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="23" MSB="3" NAME="NPI_Size" RIGHT="0" SIGNAME="npi_complete_0_XIL_NPI_Size" VECFORMULA="[3:0]"/><PORT BUS="XIL_NPI" DEF_SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_Data" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="24" MSB="63" NAME="NPI_WrFIFO_Data" RIGHT="0" SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_Data" VECFORMULA="[63:0]"/><PORT BUS="XIL_NPI" DEF_SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_BE" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="25" MSB="7" NAME="NPI_WrFIFO_BE" RIGHT="0" SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_BE" VECFORMULA="[7:0]"/><PORT BUS="XIL_NPI" DEF_SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_Push" DIR="O" MPD_INDEX="26" NAME="NPI_WrFIFO_Push" SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_Push"/><PORT BUS="XIL_NPI" DEF_SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_Data" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="27" MSB="63" NAME="NPI_RdFIFO_Data" RIGHT="0" SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_Data" VECFORMULA="[63:0]"/><PORT BUS="XIL_NPI" DEF_SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_Pop" DIR="O" MPD_INDEX="28" NAME="NPI_RdFIFO_Pop" SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_Pop"/><PORT BUS="XIL_NPI" DEF_SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_RdWdAddr" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="29" MSB="3" NAME="NPI_RdFIFO_RdWdAddr" RIGHT="0" SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_RdWdAddr" VECFORMULA="[3:0]"/><PORT BUS="XIL_NPI" DEF_SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_AlmostFull" DIR="I" MPD_INDEX="30" NAME="NPI_WrFIFO_AlmostFull" SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_AlmostFull"/><PORT BUS="XIL_NPI" DEF_SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_Flush" DIR="O" MPD_INDEX="31" NAME="NPI_WrFIFO_Flush" SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_Flush"/><PORT BUS="XIL_NPI" DEF_SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_Empty" DIR="I" MPD_INDEX="32" NAME="NPI_WrFIFO_Empty" SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_Empty"/><PORT BUS="XIL_NPI" DEF_SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_Empty" DIR="I" MPD_INDEX="33" NAME="NPI_RdFIFO_Empty" SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_Empty"/><PORT BUS="XIL_NPI" DEF_SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_Flush" DIR="O" MPD_INDEX="34" NAME="NPI_RdFIFO_Flush" SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_Flush"/><PORT BUS="XIL_NPI" DEF_SIGNAME="npi_complete_0_XIL_NPI_RdModWr" DIR="O" MPD_INDEX="35" NAME="NPI_RdModWr" SIGNAME="npi_complete_0_XIL_NPI_RdModWr"/><PORT BUS="XIL_NPI" DEF_SIGNAME="npi_complete_0_XIL_NPI_InitDone" DIR="I" MPD_INDEX="36" NAME="NPI_InitDone" SIGNAME="npi_complete_0_XIL_NPI_InitDone"/><PORT BUS="XIL_NPI" DEF_SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_Latency" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="37" MSB="1" NAME="NPI_RdFIFO_Latency" RIGHT="0" SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_Latency" VECFORMULA="[1:0]"/></PORTS><BUSINTERFACES><BUSINTERFACE BUSNAME="npi_complete_0_XIL_NPI" BUSSTD="XIL" BUSSTD_PSF="XIL_NPI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="XIL_NPI" TYPE="INITIATOR"/></BUSINTERFACES></MODULE><MODULE HWVERSION="1.00.a" INSTANCE="sata_core_0" IPTYPE="PERIPHERAL" MHS_INDEX="1" MODCLASS="PERIPHERAL" MODTYPE="sata_core"><DESCRIPTION TYPE="SHORT">SATA_CORE</DESCRIPTION><LICENSEINFO ICON_NAME="ps_core_local"/><PARAMETERS><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x70000000"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="1" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x7000FFFF"/><PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="2"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="6" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="9" NAME="C_SPLB_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="10" NAME="C_SPLB_CLK_PERIOD_PS" TYPE="INTEGER" VALUE="10000"/><PARAMETER MPD_INDEX="11" NAME="C_INCLUDE_DPHASE_TIMER" TYPE="INTEGER" VALUE="1"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6"/><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="13" NAME="CHIPSCOPE" TYPE="boolean" VALUE="true"/><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="14" NAME="DATA_WIDTH" TYPE="natural" VALUE="32"/></PARAMETERS><PORTS><PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="35" LSB="0" MHS_INDEX="0" MPD_INDEX="66" MSB="35" NAME="cmd_layer_ila_control" RIGHT="0" SIGNAME="cmd_layer_ila_control" VECFORMULA="[35:0]"/><PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="35" LSB="0" MHS_INDEX="1" MPD_INDEX="67" MSB="35" NAME="sata_rx_frame_ila_control" RIGHT="0" SIGNAME="sata_rx_frame_ila_control" VECFORMULA="[35:0]"/><PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="35" LSB="0" MHS_INDEX="2" MPD_INDEX="68" MSB="35" NAME="sata_tx_frame_ila_control" RIGHT="0" SIGNAME="sata_tx_frame_ila_control" VECFORMULA="[35:0]"/><PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="35" LSB="0" MHS_INDEX="3" MPD_INDEX="69" MSB="35" NAME="sata_phy_ila_control" RIGHT="0" SIGNAME="sata_phy_ila_control" VECFORMULA="[35:0]"/><PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="35" LSB="0" MHS_INDEX="4" MPD_INDEX="70" MSB="35" NAME="oob_control_ila_control" RIGHT="0" SIGNAME="oob_control_ila_control" VECFORMULA="[35:0]"/><PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="35" LSB="0" MHS_INDEX="5" MPD_INDEX="65" MSB="35" NAME="user_logic_ila_control" RIGHT="0" SIGNAME="user_logic_ila_control" VECFORMULA="[35:0]"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="6" MPD_INDEX="46" MSB="0" NAME="TILE0_PLLLKDET_OUT_N" RIGHT="0" SIGNAME="TILE0_PLLLKDET_OUT_N"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="7" MPD_INDEX="47" MSB="0" NAME="DCMLOCKED_OUT" RIGHT="0" SIGNAME="DCMLOCKED_OUT"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="8" MPD_INDEX="48" MSB="0" NAME="LINKUP_led" RIGHT="0" SIGNAME="LINKUP_led"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="9" MPD_INDEX="49" MSB="0" NAME="GEN2_led" RIGHT="0" SIGNAME="GEN2_led"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="10" MPD_INDEX="42" MSB="0" NAME="TXP0_OUT" RIGHT="0" SIGNAME="TXP0_OUT"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="11" MPD_INDEX="43" MSB="0" NAME="TXN0_OUT" RIGHT="0" SIGNAME="TXN0_OUT"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="12" MPD_INDEX="44" MSB="0" NAME="RXP0_IN" RIGHT="0" SIGNAME="RXP0_IN"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="13" MPD_INDEX="45" MSB="0" NAME="RXN0_IN" RIGHT="0" SIGNAME="RXN0_IN"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="14" MPD_INDEX="50" MSB="0" NAME="RESET" RIGHT="0" SIGNAME="sys_bus_reset"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="15" MPD_INDEX="51" MSB="0" NAME="CLKIN_150" RIGHT="0" SIGNAME="clk_150_0000MHz"/><PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="16" MPD_INDEX="52" MSB="31" NAME="SATA_CORE_DOUT" RIGHT="0" SIGNAME="SATA_CORE_DOUT" VECFORMULA="[31:0]"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="17" MPD_INDEX="53" MSB="0" NAME="SATA_CORE_DOUT_WE" RIGHT="0" SIGNAME="SATA_CORE_DOUT_WE"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="18" MPD_INDEX="54" MSB="0" NAME="SATA_CORE_CLK_OUT" RIGHT="0" SIGNAME="SATA_CORE_CLK_OUT"/><PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="19" MPD_INDEX="55" MSB="31" NAME="SATA_CORE_DIN" RIGHT="0" SIGNAME="SATA_CORE_DIN" VECFORMULA="[31:0]"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="20" MPD_INDEX="56" MSB="0" NAME="SATA_CORE_DIN_WE" RIGHT="0" SIGNAME="SATA_CORE_DIN_WE"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="21" MPD_INDEX="57" MSB="0" NAME="SATA_CORE_FULL" RIGHT="0" SIGNAME="SATA_CORE_FULL"/><PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="22" MPD_INDEX="58" MSB="1" NAME="NPI_CORE_REQ_TYPE" RIGHT="0" SIGNAME="NPI_CORE_REQ_TYPE" VECFORMULA="[1:0]"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="23" MPD_INDEX="59" MSB="0" NAME="NPI_CORE_NEW_CMD" RIGHT="0" SIGNAME="NPI_CORE_NEW_CMD"/><PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="24" MPD_INDEX="60" MSB="31" NAME="NPI_CORE_NUM_RD_BYTES" RIGHT="0" SIGNAME="NPI_CORE_NUM_RD_BYTES" VECFORMULA="[31:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="25" MPD_INDEX="61" MSB="31" NAME="NPI_CORE_NUM_WR_BYTES" RIGHT="0" SIGNAME="NPI_CORE_NUM_WR_BYTES" VECFORMULA="[31:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="26" MPD_INDEX="62" MSB="31" NAME="NPI_CORE_INIT_WR_ADDR" RIGHT="0" SIGNAME="NPI_CORE_INIT_WR_ADDR" VECFORMULA="[31:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="27" MPD_INDEX="63" MSB="31" NAME="NPI_CORE_INIT_RD_ADDR" RIGHT="0" SIGNAME="NPI_CORE_INIT_RD_ADDR" VECFORMULA="[31:0]"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="28" MPD_INDEX="64" MSB="0" NAME="NPI_CORE_READY_FOR_CMD" RIGHT="0" SIGNAME="NPI_CORE_READY_FOR_CMD"/><PORT BUS="SPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="8" MSB="0" NAME="PLB_masterID" RIGHT="0" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="12" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="13" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="17" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="33" MSB="0" NAME="Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="38" MSB="0" NAME="Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="39" MSB="0" NAME="Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="40" MSB="0" NAME="Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT DIR="I" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="71" MSB="35" NAME="scrambler_ila_control" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[35:0]"/><PORT DIR="I" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="72" MSB="35" NAME="descrambler_ila_control" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[35:0]"/></PORTS><BUSINTERFACES><BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/></BUSINTERFACES><MEMORYMAP><MEMRANGE BASEDECIMAL="1879048192" BASENAME="C_BASEADDR" BASEVALUE="0x70000000" HIGHDECIMAL="1879113727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7000FFFF" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K"><SLAVES><SLAVE BUSINTERFACE="SPLB"/></SLAVES></MEMRANGE></MEMORYMAP></MODULE><MODULE HWVERSION="7.30.b" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" MHS_INDEX="2" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="MICROBLAZE"><DESCRIPTION TYPE="SHORT">MicroBlaze</DESCRIPTION><DESCRIPTION TYPE="LONG">The MicroBlaze 32 bit soft processor</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="/raid/opt.x86_64/xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/doc/microblaze.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER MPD_INDEX="0" NAME="C_SCO" TYPE="integer" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FREQ" TYPE="integer" VALUE="100000000"/><PARAMETER MPD_INDEX="2" NAME="C_DATA_SIZE" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="3" NAME="C_DYNAMIC_BUS_SIZING" TYPE="integer" VALUE="1"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="virtex6"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_INSTANCE" TYPE="string" VALUE="microblaze_0"/><PARAMETER MPD_INDEX="6" NAME="C_AREA_OPTIMIZED" TYPE="integer" VALUE="0"><DESCRIPTION>Select implementation to optimize area (with lower instruction throughput)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="7" NAME="C_OPTIMIZATION" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="8" NAME="C_INTERCONNECT" TYPE="integer" VALUE="1"><DESCRIPTION>Select Bus Interfaces</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_DPLB_DWIDTH" TYPE="integer" VALUE="64"/><PARAMETER MPD_INDEX="10" NAME="C_DPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="11" NAME="C_DPLB_BURST_EN" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="12" NAME="C_DPLB_P2P" TYPE="integer" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_IPLB_DWIDTH" TYPE="integer" VALUE="64"/><PARAMETER MPD_INDEX="14" NAME="C_IPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="15" NAME="C_IPLB_BURST_EN" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="16" NAME="C_IPLB_P2P" TYPE="integer" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_D_PLB" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="18" NAME="C_D_LMB" TYPE="integer" VALUE="1"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_I_PLB" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="20" NAME="C_I_LMB" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="21" NAME="C_USE_MSR_INSTR" TYPE="integer" VALUE="1"><DESCRIPTION>Enable Additional Machine Status Register Instructions</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="22" NAME="C_USE_PCMP_INSTR" TYPE="integer" VALUE="1"><DESCRIPTION>Enable Pattern Comparator</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="23" NAME="C_USE_BARREL" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Barrel Shifter</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="24" NAME="C_USE_DIV" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Integer Divider</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="25" NAME="C_USE_HW_MUL" TYPE="integer" VALUE="1"><DESCRIPTION>Enable Integer Multiplier</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="26" NAME="C_USE_FPU" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Floating Point Unit</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="27" NAME="C_UNALIGNED_EXCEPTIONS" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Unaligned Data Exception</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="28" NAME="C_ILL_OPCODE_EXCEPTION" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Illegal Instruction Exception</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="29" NAME="C_IPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Instruction-side PLB Exception</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="30" NAME="C_DPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Data-side PLB Exception</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="31" NAME="C_DIV_ZERO_EXCEPTION" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Integer Divide Exception</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="32" NAME="C_FPU_EXCEPTION" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Floating Point Unit Exceptions</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="33" NAME="C_FSL_EXCEPTION" TYPE="integer" VALUE="0"><DESCRIPTION>Enable FSL Exception</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="34" NAME="C_PVR" TYPE="integer" VALUE="0"><DESCRIPTION>Specifies Processor Version Register</DESCRIPTION></PARAMETER><PARAMETER ENDIAN="BIG" LSB="7" MPD_INDEX="35" MSB="0" NAME="C_PVR_USER1" TYPE="std_logic_vector" VALUE="0x00"><DESCRIPTION>Specify USER1 Bits in Processor Version Register</DESCRIPTION></PARAMETER><PARAMETER ENDIAN="BIG" LSB="31" MPD_INDEX="36" MSB="0" NAME="C_PVR_USER2" TYPE="std_logic_vector" VALUE="0x00000000"><DESCRIPTION>Specify USER2 Bits in Processor Version Registers</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="37" NAME="C_DEBUG_ENABLED" TYPE="integer" VALUE="1"><DESCRIPTION>Enable MicroBlaze Debug Module Interface</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="38" NAME="C_NUMBER_OF_PC_BRK" TYPE="integer" VALUE="1"><DESCRIPTION>Number of PC Breakpoints </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="39" NAME="C_NUMBER_OF_RD_ADDR_BRK" TYPE="integer" VALUE="0"><DESCRIPTION>Number of Read Address Watchpoints </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="40" NAME="C_NUMBER_OF_WR_ADDR_BRK" TYPE="integer" VALUE="0"><DESCRIPTION>Number of Write Address Watchpoints </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="41" NAME="C_INTERRUPT_IS_EDGE" TYPE="integer" VALUE="0"><DESCRIPTION>Sense Interrupt on Edge vs. Level </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="42" NAME="C_EDGE_IS_POSITIVE" TYPE="integer" VALUE="1"><DESCRIPTION>Sense Interrupt on Rising vs. Falling Edge </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="43" NAME="C_RESET_MSR" TYPE="std_logic_vector" VALUE="0x00000000"><DESCRIPTION>Specify Reset Value for Select MSR Bits</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="44" NAME="C_OPCODE_0x0_ILLEGAL" TYPE="integer" VALUE="0"><DESCRIPTION><qt>Generate Illegal Instruction Exception for NULL Instruction</qt></DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="45" NAME="C_FSL_LINKS" TYPE="integer" VALUE="0"><DESCRIPTION>Number of FSL Links </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="46" NAME="C_FSL_DATA_SIZE" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="47" NAME="C_USE_EXTENDED_FSL_INSTR" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Additional FSL Instructions</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="NONE" MPD_INDEX="48" NAME="C_ICACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"><DESCRIPTION>I-Cache Base Address </DESCRIPTION></PARAMETER><PARAMETER ADDRESS="NONE" MPD_INDEX="49" NAME="C_ICACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0x3FFFFFFF"><DESCRIPTION>I-Cache High Address </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="50" NAME="C_USE_ICACHE" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Instruction Cache </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="51" NAME="C_ALLOW_ICACHE_WR" TYPE="integer" VALUE="1"><DESCRIPTION>Enable I-Cache Writes</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="52" NAME="C_ADDR_TAG_BITS" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="53" NAME="C_CACHE_BYTE_SIZE" TYPE="integer" VALUE="8192"><DESCRIPTION>Size of the I-Cache in Bytes</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="54" NAME="C_ICACHE_USE_FSL" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="55" NAME="C_ICACHE_LINE_LEN" TYPE="integer" VALUE="4"><DESCRIPTION>Instruction Cache Line Length</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="56" NAME="C_ICACHE_ALWAYS_USED" TYPE="integer" VALUE="0"><DESCRIPTION>Use Cache Links for All I-Cache Memory Accesses </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="57" NAME="C_ICACHE_INTERFACE" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="58" NAME="C_ICACHE_VICTIMS" TYPE="integer" VALUE="0"><DESCRIPTION>Number of I-Cache Victims</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="59" NAME="C_ICACHE_STREAMS" TYPE="integer" VALUE="0"><DESCRIPTION>Number of I-Cache Streams</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="NONE" MPD_INDEX="60" NAME="C_DCACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"><DESCRIPTION>D-Cache Base Address</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="NONE" MPD_INDEX="61" NAME="C_DCACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0x3FFFFFFF"><DESCRIPTION>D-Cache High Address</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="62" NAME="C_USE_DCACHE" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Data Cache</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="63" NAME="C_ALLOW_DCACHE_WR" TYPE="integer" VALUE="1"><DESCRIPTION>Enable D-Cache Writes</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="64" NAME="C_DCACHE_ADDR_TAG" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="65" NAME="C_DCACHE_BYTE_SIZE" TYPE="integer" VALUE="8192"><DESCRIPTION>Size of D-Cache in Bytes</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="66" NAME="C_DCACHE_USE_FSL" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="67" NAME="C_DCACHE_LINE_LEN" TYPE="integer" VALUE="4"><DESCRIPTION>Data Cache Line Length</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="68" NAME="C_DCACHE_ALWAYS_USED" TYPE="integer" VALUE="0"><DESCRIPTION>Use Cache Links for All D-Cache Memory Accesses </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="69" NAME="C_DCACHE_INTERFACE" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="70" NAME="C_DCACHE_USE_WRITEBACK" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Write-back Storage Policy</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="71" NAME="C_DCACHE_VICTIMS" TYPE="integer" VALUE="0"><DESCRIPTION>Number of D-Cache Victims</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="72" NAME="C_USE_MMU" TYPE="integer" VALUE="0"><DESCRIPTION>Memory Management</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="73" NAME="C_MMU_DTLB_SIZE" TYPE="integer" VALUE="4"><DESCRIPTION>Data Shadow Translation Look-Aside Buffer Size</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="74" NAME="C_MMU_ITLB_SIZE" TYPE="integer" VALUE="2"><DESCRIPTION>Instruction Shadow Translation Look-Aside Buffer Size</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="75" NAME="C_MMU_TLB_ACCESS" TYPE="integer" VALUE="3"><DESCRIPTION>Enable Access to Memory Management Special Registers</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="76" NAME="C_MMU_ZONES" TYPE="integer" VALUE="16"><DESCRIPTION>Number of Memory Protection Zones</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="77" NAME="C_USE_INTERRUPT" TYPE="integer" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="78" NAME="C_USE_EXT_BRK" TYPE="integer" VALUE="1"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="79" NAME="C_USE_EXT_NM_BRK" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="80" NAME="C_USE_BRANCH_TARGET_CACHE" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Branch Target Cache</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="81" NAME="C_BRANCH_TARGET_CACHE_SIZE" TYPE="integer" VALUE="0"><DESCRIPTION>Branch Target Cache Size</DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="2" MSB="0" NAME="MB_RESET" RIGHT="0" SIGIS="RST" SIGNAME="mb_reset"/><PORT BUS="DPLB:IPLB:DLMB:ILMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0"/><PORT BUS="DLMB:ILMB" DEF_SIGNAME="dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="RESET" SIGIS="RST" SIGNAME="dlmb_LMB_Rst"/><PORT DIR="I" MPD_INDEX="3" NAME="INTERRUPT" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/><PORT DEF_SIGNAME="Ext_BRK" DIR="I" MPD_INDEX="4" NAME="EXT_BRK" SIGNAME="Ext_BRK"/><PORT DEF_SIGNAME="Ext_NM_BRK" DIR="I" MPD_INDEX="5" NAME="EXT_NM_BRK" SIGNAME="Ext_NM_BRK"/><PORT DIR="I" MPD_INDEX="6" NAME="DBG_STOP" SIGNAME="__NOC__"/><PORT DIR="O" MPD_INDEX="7" NAME="MB_Halted" SIGNAME="__NOC__"/><PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="INSTR" RIGHT="31" SIGNAME="ilmb_LMB_ReadDBus" VECFORMULA="[0:31]"/><PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_Ready" DIR="I" MPD_INDEX="9" NAME="IREADY" SIGNAME="ilmb_LMB_Ready"/><PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_Wait" DIR="I" MPD_INDEX="10" NAME="IWAIT" SIGNAME="ilmb_LMB_Wait"/><PORT BUS="ILMB" DEF_SIGNAME="ilmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="INSTR_ADDR" RIGHT="31" SIGNAME="ilmb_M_ABus" VECFORMULA="[0:31]"/><PORT BUS="ILMB" DEF_SIGNAME="ilmb_M_ReadStrobe" DIR="O" MPD_INDEX="12" NAME="IFETCH" SIGNAME="ilmb_M_ReadStrobe"/><PORT BUS="ILMB" DEF_SIGNAME="ilmb_M_AddrStrobe" DIR="O" MPD_INDEX="13" NAME="I_AS" SIGNAME="ilmb_M_AddrStrobe"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_ABort" DIR="O" MPD_INDEX="14" NAME="IPLB_M_ABort" SIGNAME="mb_plb_M_ABort"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="15" MSB="0" NAME="IPLB_M_ABus" RIGHT="31" SIGNAME="mb_plb_M_ABus" VECFORMULA="[0:31]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_UABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="16" MSB="0" NAME="IPLB_M_UABus" RIGHT="31" SIGNAME="mb_plb_M_UABus" VECFORMULA="[0:31]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="17" MSB="0" NAME="IPLB_M_BE" RIGHT="7" SIGNAME="mb_plb_M_BE" VECFORMULA="[0:(C_IPLB_DWIDTH-1)/8]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_busLock" DIR="O" MPD_INDEX="18" NAME="IPLB_M_busLock" SIGNAME="mb_plb_M_busLock"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_lockErr" DIR="O" MPD_INDEX="19" NAME="IPLB_M_lockErr" SIGNAME="mb_plb_M_lockErr"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_MSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="20" MSB="0" NAME="IPLB_M_MSize" RIGHT="1" SIGNAME="mb_plb_M_MSize" VECFORMULA="[0:1]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_priority" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="21" MSB="0" NAME="IPLB_M_priority" RIGHT="1" SIGNAME="mb_plb_M_priority" VECFORMULA="[0:1]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_rdBurst" DIR="O" MPD_INDEX="22" NAME="IPLB_M_rdBurst" SIGNAME="mb_plb_M_rdBurst"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_request" DIR="O" MPD_INDEX="23" NAME="IPLB_M_request" SIGNAME="mb_plb_M_request"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_RNW" DIR="O" MPD_INDEX="24" NAME="IPLB_M_RNW" SIGNAME="mb_plb_M_RNW"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_size" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="IPLB_M_size" RIGHT="3" SIGNAME="mb_plb_M_size" VECFORMULA="[0:3]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_TAttribute" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="26" MSB="0" NAME="IPLB_M_TAttribute" RIGHT="15" SIGNAME="mb_plb_M_TAttribute" VECFORMULA="[0:15]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_type" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="IPLB_M_type" RIGHT="2" SIGNAME="mb_plb_M_type" VECFORMULA="[0:2]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_wrBurst" DIR="O" MPD_INDEX="28" NAME="IPLB_M_wrBurst" SIGNAME="mb_plb_M_wrBurst"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_wrDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="29" MSB="0" NAME="IPLB_M_wrDBus" RIGHT="63" SIGNAME="mb_plb_M_wrDBus" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MBusy" DIR="I" MPD_INDEX="30" NAME="IPLB_MBusy" SIGNAME="mb_plb_PLB_MBusy"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRdErr" DIR="I" MPD_INDEX="31" NAME="IPLB_MRdErr" SIGNAME="mb_plb_PLB_MRdErr"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MWrErr" DIR="I" MPD_INDEX="32" NAME="IPLB_MWrErr" SIGNAME="mb_plb_PLB_MWrErr"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MIRQ" DIR="I" MPD_INDEX="33" NAME="IPLB_MIRQ" SIGNAME="mb_plb_PLB_MIRQ"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MWrBTerm" DIR="I" MPD_INDEX="34" NAME="IPLB_MWrBTerm" SIGNAME="mb_plb_PLB_MWrBTerm"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MWrDAck" DIR="I" MPD_INDEX="35" NAME="IPLB_MWrDAck" SIGNAME="mb_plb_PLB_MWrDAck"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MAddrAck" DIR="I" MPD_INDEX="36" NAME="IPLB_MAddrAck" SIGNAME="mb_plb_PLB_MAddrAck"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRdBTerm" DIR="I" MPD_INDEX="37" NAME="IPLB_MRdBTerm" SIGNAME="mb_plb_PLB_MRdBTerm"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRdDAck" DIR="I" MPD_INDEX="38" NAME="IPLB_MRdDAck" SIGNAME="mb_plb_PLB_MRdDAck"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRdDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="39" MSB="0" NAME="IPLB_MRdDBus" RIGHT="63" SIGNAME="mb_plb_PLB_MRdDBus" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRdWdAddr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="40" MSB="0" NAME="IPLB_MRdWdAddr" RIGHT="3" SIGNAME="mb_plb_PLB_MRdWdAddr" VECFORMULA="[0:3]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRearbitrate" DIR="I" MPD_INDEX="41" NAME="IPLB_MRearbitrate" SIGNAME="mb_plb_PLB_MRearbitrate"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MSSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="42" MSB="0" NAME="IPLB_MSSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSSize" VECFORMULA="[0:1]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MTimeout" DIR="I" MPD_INDEX="43" NAME="IPLB_MTimeout" SIGNAME="mb_plb_PLB_MTimeout"/><PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="44" MSB="0" NAME="DATA_READ" RIGHT="31" SIGNAME="dlmb_LMB_ReadDBus" VECFORMULA="[0:31]"/><PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_Ready" DIR="I" MPD_INDEX="45" NAME="DREADY" SIGNAME="dlmb_LMB_Ready"/><PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_Wait" DIR="I" MPD_INDEX="46" NAME="DWAIT" SIGNAME="dlmb_LMB_Wait"/><PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="47" MSB="0" NAME="DATA_WRITE" RIGHT="31" SIGNAME="dlmb_M_DBus" VECFORMULA="[0:31]"/><PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="48" MSB="0" NAME="DATA_ADDR" RIGHT="31" SIGNAME="dlmb_M_ABus" VECFORMULA="[0:31]"/><PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_AddrStrobe" DIR="O" MPD_INDEX="49" NAME="D_AS" SIGNAME="dlmb_M_AddrStrobe"/><PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_ReadStrobe" DIR="O" MPD_INDEX="50" NAME="READ_STROBE" SIGNAME="dlmb_M_ReadStrobe"/><PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_WriteStrobe" DIR="O" MPD_INDEX="51" NAME="WRITE_STROBE" SIGNAME="dlmb_M_WriteStrobe"/><PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="52" MSB="0" NAME="BYTE_ENABLE" RIGHT="3" SIGNAME="dlmb_M_BE" VECFORMULA="[0:3]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_ABort" DIR="O" MPD_INDEX="53" NAME="DPLB_M_ABort" SIGNAME="mb_plb_M_ABort"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="54" MSB="0" NAME="DPLB_M_ABus" RIGHT="31" SIGNAME="mb_plb_M_ABus" VECFORMULA="[0:31]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_UABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="55" MSB="0" NAME="DPLB_M_UABus" RIGHT="31" SIGNAME="mb_plb_M_UABus" VECFORMULA="[0:31]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="56" MSB="0" NAME="DPLB_M_BE" RIGHT="7" SIGNAME="mb_plb_M_BE" VECFORMULA="[0:(C_DPLB_DWIDTH-1)/8]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_busLock" DIR="O" MPD_INDEX="57" NAME="DPLB_M_busLock" SIGNAME="mb_plb_M_busLock"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_lockErr" DIR="O" MPD_INDEX="58" NAME="DPLB_M_lockErr" SIGNAME="mb_plb_M_lockErr"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_MSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="59" MSB="0" NAME="DPLB_M_MSize" RIGHT="1" SIGNAME="mb_plb_M_MSize" VECFORMULA="[0:1]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_priority" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="60" MSB="0" NAME="DPLB_M_priority" RIGHT="1" SIGNAME="mb_plb_M_priority" VECFORMULA="[0:1]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_rdBurst" DIR="O" MPD_INDEX="61" NAME="DPLB_M_rdBurst" SIGNAME="mb_plb_M_rdBurst"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_request" DIR="O" MPD_INDEX="62" NAME="DPLB_M_request" SIGNAME="mb_plb_M_request"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_RNW" DIR="O" MPD_INDEX="63" NAME="DPLB_M_RNW" SIGNAME="mb_plb_M_RNW"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_size" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="64" MSB="0" NAME="DPLB_M_size" RIGHT="3" SIGNAME="mb_plb_M_size" VECFORMULA="[0:3]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_TAttribute" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="65" MSB="0" NAME="DPLB_M_TAttribute" RIGHT="15" SIGNAME="mb_plb_M_TAttribute" VECFORMULA="[0:15]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_type" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="66" MSB="0" NAME="DPLB_M_type" RIGHT="2" SIGNAME="mb_plb_M_type" VECFORMULA="[0:2]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_wrBurst" DIR="O" MPD_INDEX="67" NAME="DPLB_M_wrBurst" SIGNAME="mb_plb_M_wrBurst"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_wrDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="68" MSB="0" NAME="DPLB_M_wrDBus" RIGHT="63" SIGNAME="mb_plb_M_wrDBus" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MBusy" DIR="I" MPD_INDEX="69" NAME="DPLB_MBusy" SIGNAME="mb_plb_PLB_MBusy"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRdErr" DIR="I" MPD_INDEX="70" NAME="DPLB_MRdErr" SIGNAME="mb_plb_PLB_MRdErr"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MWrErr" DIR="I" MPD_INDEX="71" NAME="DPLB_MWrErr" SIGNAME="mb_plb_PLB_MWrErr"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MIRQ" DIR="I" MPD_INDEX="72" NAME="DPLB_MIRQ" SIGNAME="mb_plb_PLB_MIRQ"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MWrBTerm" DIR="I" MPD_INDEX="73" NAME="DPLB_MWrBTerm" SIGNAME="mb_plb_PLB_MWrBTerm"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MWrDAck" DIR="I" MPD_INDEX="74" NAME="DPLB_MWrDAck" SIGNAME="mb_plb_PLB_MWrDAck"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MAddrAck" DIR="I" MPD_INDEX="75" NAME="DPLB_MAddrAck" SIGNAME="mb_plb_PLB_MAddrAck"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRdBTerm" DIR="I" MPD_INDEX="76" NAME="DPLB_MRdBTerm" SIGNAME="mb_plb_PLB_MRdBTerm"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRdDAck" DIR="I" MPD_INDEX="77" NAME="DPLB_MRdDAck" SIGNAME="mb_plb_PLB_MRdDAck"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRdDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="78" MSB="0" NAME="DPLB_MRdDBus" RIGHT="63" SIGNAME="mb_plb_PLB_MRdDBus" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRdWdAddr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="79" MSB="0" NAME="DPLB_MRdWdAddr" RIGHT="3" SIGNAME="mb_plb_PLB_MRdWdAddr" VECFORMULA="[0:3]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRearbitrate" DIR="I" MPD_INDEX="80" NAME="DPLB_MRearbitrate" SIGNAME="mb_plb_PLB_MRearbitrate"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MSSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="81" MSB="0" NAME="DPLB_MSSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSSize" VECFORMULA="[0:1]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MTimeout" DIR="I" MPD_INDEX="82" NAME="DPLB_MTimeout" SIGNAME="mb_plb_PLB_MTimeout"/><PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Clk" DIR="I" MPD_INDEX="83" NAME="DBG_CLK" SIGNAME="microblaze_0_mdm_bus_Dbg_Clk"/><PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_TDI" DIR="I" MPD_INDEX="84" NAME="DBG_TDI" SIGNAME="microblaze_0_mdm_bus_Dbg_TDI"/><PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_TDO" DIR="O" MPD_INDEX="85" NAME="DBG_TDO" SIGNAME="microblaze_0_mdm_bus_Dbg_TDO"/><PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Reg_En" DIR="I" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="86" MSB="0" NAME="DBG_REG_EN" RIGHT="4" SIGNAME="microblaze_0_mdm_bus_Dbg_Reg_En" VECFORMULA="[0:4]"/><PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Shift" DIR="I" MPD_INDEX="87" NAME="DBG_SHIFT" SIGNAME="microblaze_0_mdm_bus_Dbg_Shift"/><PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Capture" DIR="I" MPD_INDEX="88" NAME="DBG_CAPTURE" SIGNAME="microblaze_0_mdm_bus_Dbg_Capture"/><PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Update" DIR="I" MPD_INDEX="89" NAME="DBG_UPDATE" SIGNAME="microblaze_0_mdm_bus_Dbg_Update"/><PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_mdm_bus_Debug_Rst" DIR="I" MPD_INDEX="90" NAME="DEBUG_RST" SIGIS="RST" SIGNAME="microblaze_0_mdm_bus_Debug_Rst"/><PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" 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NAME="MFSL2" TYPE="MASTER"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="10" NAME="SFSL3" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="11" NAME="MFSL3" TYPE="MASTER"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="12" NAME="SFSL4" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="13" NAME="MFSL4" TYPE="MASTER"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="14" NAME="SFSL5" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="15" NAME="MFSL5" TYPE="MASTER"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="16" NAME="SFSL6" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="17" NAME="MFSL6" TYPE="MASTER"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="18" NAME="SFSL7" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="19" NAME="MFSL7" TYPE="MASTER"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="20" NAME="SFSL8" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="21" NAME="MFSL8" TYPE="MASTER"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="22" NAME="SFSL9" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="23" NAME="MFSL9" TYPE="MASTER"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="24" NAME="SFSL10" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="25" NAME="MFSL10" TYPE="MASTER"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="26" NAME="SFSL11" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="27" NAME="MFSL11" TYPE="MASTER"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="28" NAME="SFSL12" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="29" NAME="MFSL12" TYPE="MASTER"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="30" NAME="SFSL13" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="31" NAME="MFSL13" TYPE="MASTER"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="32" NAME="SFSL14" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="33" NAME="MFSL14" TYPE="MASTER"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="34" NAME="SFSL15" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="35" NAME="MFSL15" TYPE="MASTER"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="36" NAME="DRFSL0" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="37" NAME="DWFSL0" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="38" NAME="DRFSL1" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="39" NAME="DWFSL1" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="40" NAME="DRFSL2" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="41" NAME="DWFSL2" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="42" NAME="DRFSL3" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="43" NAME="DWFSL3" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="44" NAME="DRFSL4" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="45" NAME="DWFSL4" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="46" NAME="DRFSL5" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="47" NAME="DWFSL5" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="48" NAME="DRFSL6" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="49" NAME="DWFSL6" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="50" NAME="DRFSL7" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="51" NAME="DWFSL7" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="52" NAME="DRFSL8" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="53" NAME="DWFSL8" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="54" NAME="DRFSL9" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="55" NAME="DWFSL9" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="56" NAME="DRFSL10" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="57" NAME="DWFSL10" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="58" NAME="DRFSL11" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="59" NAME="DWFSL11" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="60" NAME="DRFSL12" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="61" NAME="DWFSL12" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="62" NAME="DRFSL13" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="63" NAME="DWFSL13" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="64" NAME="DRFSL14" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="65" NAME="DWFSL14" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="66" NAME="DRFSL15" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="67" NAME="DWFSL15" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_DATA="TRUE" MPD_INDEX="68" NAME="DXCL" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_INSTRUCTION="TRUE" MPD_INDEX="69" NAME="IXCL" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBTRACE2" MPD_INDEX="71" NAME="TRACE" TYPE="INITIATOR"/></BUSINTERFACES><MEMORYMAP><MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="262143" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x0003FFFF" INSTANCE="dlmb_cntlr" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="262144" SIZEABRV="256K"><ACCESSROUTE><ROUTEPNT INDEX="0" INSTANCE="dlmb"/></ACCESSROUTE></MEMRANGE><MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="262143" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x0003FFFF" INSTANCE="ilmb_cntlr" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="262144" SIZEABRV="256K"><ACCESSROUTE><ROUTEPNT INDEX="0" INSTANCE="ilmb"/></ACCESSROUTE></MEMRANGE><MEMRANGE BASEDECIMAL="1879048192" BASENAME="C_BASEADDR" BASEVALUE="0x70000000" HIGHDECIMAL="1879113727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7000FFFF" INSTANCE="sata_core_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"><ACCESSROUTE><ROUTEPNT INDEX="0" INSTANCE="mb_plb"/></ACCESSROUTE></MEMRANGE><MEMRANGE BASEDECIMAL="2214592512" BASENAME="C_BASEADDR" BASEVALUE="0x84000000" HIGHDECIMAL="2214658047" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8400ffff" INSTANCE="RS232_Uart_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"><ACCESSROUTE><ROUTEPNT INDEX="0" INSTANCE="mb_plb"/></ACCESSROUTE></MEMRANGE><MEMRANGE BASEDECIMAL="2415919104" BASENAME="C_MPMC_BASEADDR" BASEVALUE="0x90000000" HIGHDECIMAL="2684354559" HIGHNAME="C_MPMC_HIGHADDR" HIGHVALUE="0x9fffffff" INSTANCE="DDR3_SDRAM" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="268435456" SIZEABRV="256M"><ACCESSROUTE><ROUTEPNT INDEX="0" INSTANCE="mb_plb"/></ACCESSROUTE></MEMRANGE><MEMRANGE BASEDECIMAL="2218786816" BASENAME="C_BASEADDR" BASEVALUE="0x84400000" HIGHDECIMAL="2218852351" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8440ffff" INSTANCE="mdm_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"><ACCESSROUTE><ROUTEPNT INDEX="0" INSTANCE="mb_plb"/></ACCESSROUTE></MEMRANGE></MEMORYMAP><PERIPHERALS><PERIPHERAL INSTANCE="dlmb_cntlr"/><PERIPHERAL INSTANCE="ilmb_cntlr"/><PERIPHERAL INSTANCE="sata_core_0"/><PERIPHERAL INSTANCE="RS232_Uart_1"/><PERIPHERAL INSTANCE="DDR3_SDRAM"/><PERIPHERAL INSTANCE="mdm_0"/></PERIPHERALS></MODULE><MODULE BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" HWVERSION="1.04.a" INSTANCE="mb_plb" IPTYPE="BUS" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="plb_v46"><DESCRIPTION TYPE="SHORT">Processor Local Bus (PLB) 4.6</DESCRIPTION><DESCRIPTION TYPE="LONG">'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature'</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="/raid/opt.x86_64/xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plb_v46_v1_04_a/doc/plb_v46.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_PLBV46_NUM_MASTERS" TYPE="integer" VALUE="2"><DESCRIPTION>Number of PLB Masters</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_PLBV46_NUM_SLAVES" TYPE="integer" VALUE="4"><DESCRIPTION>Number of PLB Slaves</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PLBV46_MID_WIDTH" TYPE="integer" VALUE="1"><DESCRIPTION>PLB Master ID Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="3" NAME="C_PLBV46_AWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>PLB Address Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="4" NAME="C_PLBV46_DWIDTH" TYPE="integer" VALUE="64"><DESCRIPTION>PLB Data Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="5" NAME="C_DCR_INTFCE" TYPE="integer" VALUE="0"><DESCRIPTION>Include DCR Interface and Error Registers</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="6" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0b1111111111"><DESCRIPTION>Base Address</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="7" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0b0000000000"><DESCRIPTION>High Address</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="8" NAME="C_DCR_AWIDTH" TYPE="integer" VALUE="10"><DESCRIPTION>DCR Address Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="9" NAME="C_DCR_DWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>DCR Data Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="10" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1"><DESCRIPTION>External Reset Active High </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="11" NAME="C_IRQ_ACTIVE" TYPE="std_logic" VALUE="1"><DESCRIPTION>IRQ Active State </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="12" NAME="C_NUM_CLK_PLB2OPB_REARB" TYPE="integer" VALUE="5"><DESCRIPTION><qt>Number of PLB Clock Periods a PLB Master that Received a Rearbitrate from an OPB2PLB Bridge on a Read Operation is Denied Grant on the PLB Bus</qt></DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="13" NAME="C_ADDR_PIPELINING_TYPE" TYPE="integer" VALUE="1"><DESCRIPTION>Enable Address Pipelining Type</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="14" NAME="C_FAMILY" TYPE="string" VALUE="virtex6"><DESCRIPTION>Device Family</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="15" NAME="C_P2P" TYPE="integer" VALUE="0"><DESCRIPTION>Optimize PLB for Point-to-point Topology</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="16" NAME="C_ARB_TYPE" TYPE="integer" VALUE="0"><DESCRIPTION>Selects the Arbitration Scheme</DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT CLKFREQUENCY="100000000" DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="0" MSB="0" NAME="PLB_Clk" RIGHT="0" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="1" MPD_INDEX="1" MSB="0" NAME="SYS_Rst" RIGHT="0" SIGIS="RST" SIGNAME="sys_bus_reset"/><PORT DEF_SIGNAME="mb_plb_PLB_Rst" DIR="O" MPD_INDEX="2" NAME="PLB_Rst" SIGIS="RST" SIGNAME="mb_plb_PLB_Rst"/><PORT DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="3" MSB="0" NAME="SPLB_Rst" RIGHT="3" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_MPLB_Rst" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="4" MSB="0" NAME="MPLB_Rst" RIGHT="1" SIGIS="RST" SIGNAME="mb_plb_MPLB_Rst" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="5" NAME="PLB_dcrAck" SIGNAME="__NOC__"/><PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="PLB_dcrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DCR_DWIDTH-1]"/><PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="9" MPD_INDEX="7" MSB="0" NAME="DCR_ABus" RIGHT="9" SIGNAME="__NOC__" VECFORMULA="[0:C_DCR_AWIDTH-1]"/><PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="DCR_DBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DCR_DWIDTH-1]"/><PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="DCR_Read" SIGNAME="__NOC__"/><PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="10" NAME="DCR_Write" SIGNAME="__NOC__"/><PORT DEF_SIGNAME="mb_plb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="11" MSB="0" NAME="M_ABus" RIGHT="63" SIGNAME="mb_plb_M_ABus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*32)-1]"/><PORT DEF_SIGNAME="mb_plb_M_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="12" MSB="0" NAME="M_UABus" RIGHT="63" SIGNAME="mb_plb_M_UABus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*32)-1]"/><PORT DEF_SIGNAME="mb_plb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="13" MSB="0" NAME="M_BE" RIGHT="15" SIGNAME="mb_plb_M_BE" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1]"/><PORT DEF_SIGNAME="mb_plb_M_RNW" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="14" MSB="0" NAME="M_RNW" RIGHT="1" SIGNAME="mb_plb_M_RNW" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_M_abort" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="15" MSB="0" NAME="M_abort" RIGHT="1" SIGNAME="mb_plb_M_abort" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_M_busLock" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="16" MSB="0" NAME="M_busLock" RIGHT="1" SIGNAME="mb_plb_M_busLock" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_M_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="M_TAttribute" RIGHT="31" SIGNAME="mb_plb_M_TAttribute" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*16)-1]"/><PORT DEF_SIGNAME="mb_plb_M_lockErr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="18" MSB="0" NAME="M_lockErr" RIGHT="1" SIGNAME="mb_plb_M_lockErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_M_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="19" MSB="0" NAME="M_MSize" RIGHT="3" SIGNAME="mb_plb_M_MSize" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*2)-1]"/><PORT DEF_SIGNAME="mb_plb_M_priority" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="20" MSB="0" NAME="M_priority" RIGHT="3" SIGNAME="mb_plb_M_priority" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*2)-1]"/><PORT DEF_SIGNAME="mb_plb_M_rdBurst" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="21" MSB="0" NAME="M_rdBurst" RIGHT="1" SIGNAME="mb_plb_M_rdBurst" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_M_request" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="M_request" RIGHT="1" SIGNAME="mb_plb_M_request" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_M_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="23" MSB="0" NAME="M_size" RIGHT="7" SIGNAME="mb_plb_M_size" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*4)-1]"/><PORT DEF_SIGNAME="mb_plb_M_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="5" MPD_INDEX="24" MSB="0" NAME="M_type" RIGHT="5" SIGNAME="mb_plb_M_type" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*3)-1]"/><PORT DEF_SIGNAME="mb_plb_M_wrBurst" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="25" MSB="0" NAME="M_wrBurst" RIGHT="1" SIGNAME="mb_plb_M_wrBurst" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_M_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="127" MPD_INDEX="26" MSB="0" NAME="M_wrDBus" RIGHT="127" SIGNAME="mb_plb_M_wrDBus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="27" MSB="0" NAME="Sl_addrAck" RIGHT="3" SIGNAME="mb_plb_Sl_addrAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="28" MSB="0" NAME="Sl_MRdErr" RIGHT="7" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="29" MSB="0" NAME="Sl_MWrErr" RIGHT="7" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="30" MSB="0" NAME="Sl_MBusy" RIGHT="7" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 ]"/><PORT DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="31" MSB="0" NAME="Sl_rdBTerm" RIGHT="3" SIGNAME="mb_plb_Sl_rdBTerm" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="32" MSB="0" NAME="Sl_rdComp" RIGHT="3" SIGNAME="mb_plb_Sl_rdComp" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="33" MSB="0" NAME="Sl_rdDAck" RIGHT="3" SIGNAME="mb_plb_Sl_rdDAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="255" MPD_INDEX="34" MSB="0" NAME="Sl_rdDBus" RIGHT="255" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="35" MSB="0" NAME="Sl_rdWdAddr" RIGHT="15" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*4-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="36" MSB="0" NAME="Sl_rearbitrate" RIGHT="3" SIGNAME="mb_plb_Sl_rearbitrate" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_SSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="37" MSB="0" NAME="Sl_SSize" RIGHT="7" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*2-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_wait" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="38" MSB="0" NAME="Sl_wait" RIGHT="3" SIGNAME="mb_plb_Sl_wait" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="39" MSB="0" NAME="Sl_wrBTerm" RIGHT="3" SIGNAME="mb_plb_Sl_wrBTerm" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="40" MSB="0" NAME="Sl_wrComp" RIGHT="3" SIGNAME="mb_plb_Sl_wrComp" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="41" MSB="0" NAME="Sl_wrDAck" RIGHT="3" SIGNAME="mb_plb_Sl_wrDAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="42" MSB="0" NAME="Sl_MIRQ" RIGHT="7" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="43" MSB="0" NAME="PLB_MIRQ" RIGHT="1" SIGNAME="mb_plb_PLB_MIRQ" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="44" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/><PORT DEF_SIGNAME="mb_plb_PLB_UABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="45" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/><PORT DEF_SIGNAME="mb_plb_PLB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="46" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:(C_PLBV46_DWIDTH/8)-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MAddrAck" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="PLB_MAddrAck" RIGHT="1" SIGNAME="mb_plb_PLB_MAddrAck" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MTimeout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="48" MSB="0" NAME="PLB_MTimeout" RIGHT="1" SIGNAME="mb_plb_PLB_MTimeout" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="49" MSB="0" NAME="PLB_MBusy" RIGHT="1" SIGNAME="mb_plb_PLB_MBusy" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="50" MSB="0" NAME="PLB_MRdErr" RIGHT="1" SIGNAME="mb_plb_PLB_MRdErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="51" MSB="0" NAME="PLB_MWrErr" RIGHT="1" SIGNAME="mb_plb_PLB_MWrErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MRdBTerm" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="52" MSB="0" NAME="PLB_MRdBTerm" RIGHT="1" SIGNAME="mb_plb_PLB_MRdBTerm" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MRdDAck" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="PLB_MRdDAck" RIGHT="1" SIGNAME="mb_plb_PLB_MRdDAck" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MRdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="127" MPD_INDEX="54" MSB="0" NAME="PLB_MRdDBus" RIGHT="127" SIGNAME="mb_plb_PLB_MRdDBus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MRdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="55" MSB="0" NAME="PLB_MRdWdAddr" RIGHT="7" SIGNAME="mb_plb_PLB_MRdWdAddr" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*4)-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MRearbitrate" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="56" MSB="0" NAME="PLB_MRearbitrate" RIGHT="1" SIGNAME="mb_plb_PLB_MRearbitrate" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MWrBTerm" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="57" MSB="0" NAME="PLB_MWrBTerm" RIGHT="1" SIGNAME="mb_plb_PLB_MWrBTerm" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MWrDAck" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="58" MSB="0" NAME="PLB_MWrDAck" RIGHT="1" SIGNAME="mb_plb_PLB_MWrDAck" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MSSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="59" MSB="0" NAME="PLB_MSSize" RIGHT="3" SIGNAME="mb_plb_PLB_MSSize" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*2)-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="O" MPD_INDEX="60" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/><PORT DEF_SIGNAME="mb_plb_PLB_RNW" DIR="O" MPD_INDEX="61" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/><PORT DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="O" MPD_INDEX="62" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/><PORT DEF_SIGNAME="mb_plb_PLB_abort" DIR="O" MPD_INDEX="63" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/><PORT DEF_SIGNAME="mb_plb_PLB_busLock" DIR="O" MPD_INDEX="64" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/><PORT DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="65" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/><PORT DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="O" MPD_INDEX="66" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/><PORT DEF_SIGNAME="mb_plb_PLB_masterID" DIR="O" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="67" MSB="0" NAME="PLB_masterID" RIGHT="0" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:C_PLBV46_MID_WIDTH-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="68" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/><PORT DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="69" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/><PORT DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="70" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/><PORT DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="O" MPD_INDEX="71" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/><PORT DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="O" MPD_INDEX="72" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/><PORT DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="O" MPD_INDEX="73" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/><PORT DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="74" MSB="0" NAME="PLB_rdPrim" RIGHT="3" SIGNAME="mb_plb_PLB_rdPrim" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="75" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/><PORT DEF_SIGNAME="mb_plb_PLB_size" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="76" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/><PORT DEF_SIGNAME="mb_plb_PLB_type" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="77" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/><PORT DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="O" MPD_INDEX="78" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/><PORT DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="79" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:C_PLBV46_DWIDTH-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="80" MSB="0" NAME="PLB_wrPrim" RIGHT="3" SIGNAME="mb_plb_PLB_wrPrim" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_SaddrAck" DIR="O" MPD_INDEX="81" NAME="PLB_SaddrAck" SIGNAME="mb_plb_PLB_SaddrAck"/><PORT DEF_SIGNAME="mb_plb_PLB_SMRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="82" MSB="0" NAME="PLB_SMRdErr" RIGHT="1" SIGNAME="mb_plb_PLB_SMRdErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_SMWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="83" MSB="0" NAME="PLB_SMWrErr" RIGHT="1" SIGNAME="mb_plb_PLB_SMWrErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_SMBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="84" MSB="0" NAME="PLB_SMBusy" RIGHT="1" SIGNAME="mb_plb_PLB_SMBusy" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_SrdBTerm" DIR="O" MPD_INDEX="85" NAME="PLB_SrdBTerm" SIGNAME="mb_plb_PLB_SrdBTerm"/><PORT DEF_SIGNAME="mb_plb_PLB_SrdComp" DIR="O" MPD_INDEX="86" NAME="PLB_SrdComp" SIGNAME="mb_plb_PLB_SrdComp"/><PORT DEF_SIGNAME="mb_plb_PLB_SrdDAck" DIR="O" MPD_INDEX="87" NAME="PLB_SrdDAck" SIGNAME="mb_plb_PLB_SrdDAck"/><PORT DEF_SIGNAME="mb_plb_PLB_SrdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="88" MSB="0" NAME="PLB_SrdDBus" RIGHT="63" SIGNAME="mb_plb_PLB_SrdDBus" VECFORMULA="[0:C_PLBV46_DWIDTH-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_SrdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="89" MSB="0" NAME="PLB_SrdWdAddr" RIGHT="3" SIGNAME="mb_plb_PLB_SrdWdAddr" VECFORMULA="[0:3]"/><PORT DEF_SIGNAME="mb_plb_PLB_Srearbitrate" DIR="O" MPD_INDEX="90" NAME="PLB_Srearbitrate" SIGNAME="mb_plb_PLB_Srearbitrate"/><PORT DEF_SIGNAME="mb_plb_PLB_Sssize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="91" MSB="0" NAME="PLB_Sssize" RIGHT="1" SIGNAME="mb_plb_PLB_Sssize" VECFORMULA="[0:1]"/><PORT DEF_SIGNAME="mb_plb_PLB_Swait" DIR="O" MPD_INDEX="92" NAME="PLB_Swait" SIGNAME="mb_plb_PLB_Swait"/><PORT DEF_SIGNAME="mb_plb_PLB_SwrBTerm" DIR="O" MPD_INDEX="93" NAME="PLB_SwrBTerm" SIGNAME="mb_plb_PLB_SwrBTerm"/><PORT DEF_SIGNAME="mb_plb_PLB_SwrComp" DIR="O" MPD_INDEX="94" NAME="PLB_SwrComp" SIGNAME="mb_plb_PLB_SwrComp"/><PORT DEF_SIGNAME="mb_plb_PLB_SwrDAck" DIR="O" MPD_INDEX="95" NAME="PLB_SwrDAck" SIGNAME="mb_plb_PLB_SwrDAck"/><PORT DIR="O" MPD_INDEX="96" NAME="Bus_Error_Det" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/></PORTS><BUSINTERFACES><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="DCR" BUSSTD_PSF="DCR" IS_VALID="FALSE" MPD_INDEX="0" NAME="SDCR" TYPE="SLAVE"/></BUSINTERFACES><MEMORYMAP><MEMRANGE BASEDECIMAL="1023" BASENAME="C_BASEADDR" BASEVALUE="0b1111111111" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0b0000000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x08" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="SDCR"/></SLAVES></MEMRANGE></MEMORYMAP></MODULE><MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="1.00.a" INSTANCE="ilmb" IPTYPE="BUS" MHS_INDEX="4" MODCLASS="BUS" MODTYPE="lmb_v10"><DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION><DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="/raid/opt.x86_64/xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/doc/lmb_v10.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1"><DESCRIPTION>Number of Bus Slaves </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>LMB Address Bus Width </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>LMB Data Bus Width </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1"><DESCRIPTION>Active High External Reset</DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT CLKFREQUENCY="100000000" DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="0" MSB="0" NAME="LMB_Clk" RIGHT="0" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="1" MPD_INDEX="1" MSB="0" NAME="SYS_Rst" RIGHT="0" SIGNAME="sys_bus_reset"/><PORT DEF_SIGNAME="ilmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="ilmb_LMB_Rst"/><PORT DEF_SIGNAME="ilmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="ilmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/><PORT DEF_SIGNAME="ilmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="ilmb_M_ReadStrobe"/><PORT DEF_SIGNAME="ilmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="ilmb_M_WriteStrobe"/><PORT DEF_SIGNAME="ilmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="ilmb_M_AddrStrobe"/><PORT DEF_SIGNAME="ilmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="ilmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT DEF_SIGNAME="ilmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="ilmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/><PORT DEF_SIGNAME="ilmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="ilmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/><PORT DEF_SIGNAME="ilmb_Sl_Ready" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="10" MSB="0" NAME="Sl_Ready" RIGHT="0" SIGNAME="ilmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="ilmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/><PORT DEF_SIGNAME="ilmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="12" NAME="LMB_ReadStrobe" SIGNAME="ilmb_LMB_ReadStrobe"/><PORT DEF_SIGNAME="ilmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="13" NAME="LMB_WriteStrobe" SIGNAME="ilmb_LMB_WriteStrobe"/><PORT DEF_SIGNAME="ilmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="14" NAME="LMB_AddrStrobe" SIGNAME="ilmb_LMB_AddrStrobe"/><PORT DEF_SIGNAME="ilmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="15" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="ilmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT DEF_SIGNAME="ilmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="16" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT DEF_SIGNAME="ilmb_LMB_Ready" DIR="O" MPD_INDEX="17" NAME="LMB_Ready" SIGNAME="ilmb_LMB_Ready"/><PORT DEF_SIGNAME="ilmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="18" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="ilmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/></PORTS><BUSINTERFACES/></MODULE><MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="1.00.a" INSTANCE="dlmb" IPTYPE="BUS" MHS_INDEX="5" MODCLASS="BUS" MODTYPE="lmb_v10"><DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION><DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="/raid/opt.x86_64/xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/doc/lmb_v10.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1"><DESCRIPTION>Number of Bus Slaves </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>LMB Address Bus Width </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>LMB Data Bus Width </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1"><DESCRIPTION>Active High External Reset</DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT CLKFREQUENCY="100000000" DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="0" MSB="0" NAME="LMB_Clk" RIGHT="0" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="1" MPD_INDEX="1" MSB="0" NAME="SYS_Rst" RIGHT="0" SIGNAME="sys_bus_reset"/><PORT DEF_SIGNAME="dlmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="dlmb_LMB_Rst"/><PORT DEF_SIGNAME="dlmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="dlmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/><PORT DEF_SIGNAME="dlmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="dlmb_M_ReadStrobe"/><PORT DEF_SIGNAME="dlmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="dlmb_M_WriteStrobe"/><PORT DEF_SIGNAME="dlmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="dlmb_M_AddrStrobe"/><PORT DEF_SIGNAME="dlmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="dlmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT DEF_SIGNAME="dlmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="dlmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/><PORT DEF_SIGNAME="dlmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="dlmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/><PORT DEF_SIGNAME="dlmb_Sl_Ready" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="10" MSB="0" NAME="Sl_Ready" RIGHT="0" SIGNAME="dlmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="dlmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/><PORT DEF_SIGNAME="dlmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="12" NAME="LMB_ReadStrobe" SIGNAME="dlmb_LMB_ReadStrobe"/><PORT DEF_SIGNAME="dlmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="13" NAME="LMB_WriteStrobe" SIGNAME="dlmb_LMB_WriteStrobe"/><PORT DEF_SIGNAME="dlmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="14" NAME="LMB_AddrStrobe" SIGNAME="dlmb_LMB_AddrStrobe"/><PORT DEF_SIGNAME="dlmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="15" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="dlmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT DEF_SIGNAME="dlmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="16" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT DEF_SIGNAME="dlmb_LMB_Ready" DIR="O" MPD_INDEX="17" NAME="LMB_Ready" SIGNAME="dlmb_LMB_Ready"/><PORT DEF_SIGNAME="dlmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="18" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="dlmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/></PORTS><BUSINTERFACES/></MODULE><MODULE HWVERSION="2.10.b" INSTANCE="dlmb_cntlr" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr"><DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION><DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="/raid/opt.x86_64/xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v2_10_b/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"><DESCRIPTION>LMB BRAM Base Address</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x0003FFFF"><DESCRIPTION>LMB BRAM High Address</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" ENDIAN="BIG" LSB="31" MPD_INDEX="2" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x14000000"><DESCRIPTION>LMB Address Decode Mask</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="3" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>LMB Address Bus Width </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="4" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>LMB Data Bus Width </DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="dlmb_LMB_Rst"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="dlmb_LMB_AddrStrobe"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="dlmb_LMB_ReadStrobe"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="dlmb_LMB_WriteStrobe"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="dlmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="dlmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="dlmb_Sl_Ready"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Rst" DIR="O" MPD_INDEX="10" NAME="BRAM_Rst_A" SIGNAME="dlmb_port_BRAM_Rst"/><PORT BUS="BRAM_PORT" CLKFREQUENCY="100000000" DEF_SIGNAME="dlmb_port_BRAM_Clk" DIR="O" MPD_INDEX="11" NAME="BRAM_Clk_A" SIGNAME="dlmb_port_BRAM_Clk"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_EN" DIR="O" MPD_INDEX="12" NAME="BRAM_EN_A" SIGNAME="dlmb_port_BRAM_EN"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="13" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="dlmb_port_BRAM_WEN" VECFORMULA="[0:(C_LMB_DWIDTH/8)-1]"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="dlmb_port_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="15" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="dlmb_port_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="16" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="dlmb_port_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1]"/></PORTS><BUSINTERFACES><BUSINTERFACE BUSNAME="dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="dlmb_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR"/></BUSINTERFACES><MEMORYMAP><MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="262143" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x0003FFFF" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="262144" SIZEABRV="256K"><SLAVES><SLAVE BUSINTERFACE="SLMB"/></SLAVES></MEMRANGE></MEMORYMAP></MODULE><MODULE HWVERSION="2.10.b" INSTANCE="ilmb_cntlr" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr"><DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION><DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="/raid/opt.x86_64/xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v2_10_b/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"><DESCRIPTION>LMB BRAM Base Address</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x0003FFFF"><DESCRIPTION>LMB BRAM High Address</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" ENDIAN="BIG" LSB="31" MPD_INDEX="2" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x14000000"><DESCRIPTION>LMB Address Decode Mask</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="3" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>LMB Address Bus Width </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="4" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>LMB Data Bus Width </DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="ilmb_LMB_Rst"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="ilmb_LMB_AddrStrobe"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="ilmb_LMB_ReadStrobe"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="ilmb_LMB_WriteStrobe"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="ilmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="ilmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="ilmb_Sl_Ready"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Rst" DIR="O" MPD_INDEX="10" NAME="BRAM_Rst_A" SIGNAME="ilmb_port_BRAM_Rst"/><PORT BUS="BRAM_PORT" CLKFREQUENCY="100000000" DEF_SIGNAME="ilmb_port_BRAM_Clk" DIR="O" MPD_INDEX="11" NAME="BRAM_Clk_A" SIGNAME="ilmb_port_BRAM_Clk"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_EN" DIR="O" MPD_INDEX="12" NAME="BRAM_EN_A" SIGNAME="ilmb_port_BRAM_EN"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="13" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="ilmb_port_BRAM_WEN" VECFORMULA="[0:(C_LMB_DWIDTH/8)-1]"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="15" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="16" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1]"/></PORTS><BUSINTERFACES><BUSINTERFACE BUSNAME="ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="ilmb_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR"/></BUSINTERFACES><MEMORYMAP><MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="262143" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x0003FFFF" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="262144" SIZEABRV="256K"><SLAVES><SLAVE BUSINTERFACE="SLMB"/></SLAVES></MEMRANGE></MEMORYMAP></MODULE><MODULE HWVERSION="1.00.a" INSTANCE="lmb_bram" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="MEMORY" MODTYPE="bram_block"><DESCRIPTION TYPE="SHORT">Block RAM (BRAM) Block</DESCRIPTION><DESCRIPTION TYPE="LONG">The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="/raid/opt.x86_64/xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/doc/bram_block.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_MEMSIZE" TYPE="integer" VALUE="0x40000"><DESCRIPTION>Size of BRAM(s) in Bytes</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="1" NAME="C_PORT_DWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>Data Width of Port A and B</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="2" NAME="C_PORT_AWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>Address Width of Port A and B</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="3" NAME="C_NUM_WE" TYPE="integer" VALUE="4"><DESCRIPTION>Number of Byte Write Enables</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="virtex6"><DESCRIPTION>Device Family</DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Rst" DIR="I" MPD_INDEX="0" NAME="BRAM_Rst_A" SIGNAME="ilmb_port_BRAM_Rst"/><PORT BUS="PORTA" CLKFREQUENCY="100000000" DEF_SIGNAME="ilmb_port_BRAM_Clk" DIR="I" MPD_INDEX="1" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="ilmb_port_BRAM_Clk"/><PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_EN" DIR="I" MPD_INDEX="2" NAME="BRAM_EN_A" SIGNAME="ilmb_port_BRAM_EN"/><PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="3" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="ilmb_port_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/><PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/><PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="5" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/><PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/><PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Rst" DIR="I" MPD_INDEX="7" NAME="BRAM_Rst_B" SIGNAME="dlmb_port_BRAM_Rst"/><PORT BUS="PORTB" CLKFREQUENCY="100000000" DEF_SIGNAME="dlmb_port_BRAM_Clk" DIR="I" MPD_INDEX="8" NAME="BRAM_Clk_B" SIGIS="CLK" SIGNAME="dlmb_port_BRAM_Clk"/><PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_EN" DIR="I" MPD_INDEX="9" NAME="BRAM_EN_B" SIGNAME="dlmb_port_BRAM_EN"/><PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="10" MSB="0" NAME="BRAM_WEN_B" RIGHT="3" SIGNAME="dlmb_port_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/><PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="BRAM_Addr_B" RIGHT="31" SIGNAME="dlmb_port_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/><PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="BRAM_Din_B" RIGHT="31" SIGNAME="dlmb_port_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/><PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="13" MSB="0" NAME="BRAM_Dout_B" RIGHT="31" SIGNAME="dlmb_port_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/></PORTS><BUSINTERFACES><BUSINTERFACE BUSNAME="ilmb_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PORTA" TYPE="TARGET"/><BUSINTERFACE BUSNAME="dlmb_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="PORTB" TYPE="TARGET"/></BUSINTERFACES></MODULE><MODULE HWVERSION="1.01.a" INSTANCE="RS232_Uart_1" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="PERIPHERAL" MODTYPE="xps_uartlite"><DESCRIPTION TYPE="SHORT">XPS UART (Lite)</DESCRIPTION><DESCRIPTION TYPE="LONG">Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus.</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="/raid/opt.x86_64/xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_uartlite_v1_01_a/doc/xps_uartlite.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6"><DESCRIPTION>Device Family</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="1" NAME="C_SPLB_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"><DESCRIPTION>Clock Frequency of PLB Slave</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="6" MPD_INDEX="2" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x84000000"><DESCRIPTION>Base Address</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="7" MPD_INDEX="3" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8400ffff"><DESCRIPTION>High Address</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="4" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>PLB Address Bus Width</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="64"><DESCRIPTION>PLB Data Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="6" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"><DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="7" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"><DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="2"><DESCRIPTION>Number of PLB Masters</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="9" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"><DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="10" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="11" NAME="C_BAUDRATE" TYPE="INTEGER" VALUE="115200"><DESCRIPTION>UART Lite Baud Rate </DESCRIPTION><DESCRIPTION>Baud Rate</DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="12" NAME="C_DATA_BITS" TYPE="INTEGER" VALUE="8"><DESCRIPTION>Number of Data Bits in a Serial Frame</DESCRIPTION><DESCRIPTION>Data Bits</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="13" NAME="C_USE_PARITY" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Use Parity </DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="14" NAME="C_ODD_PARITY" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Parity Type </DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="42" MSB="0" NAME="RX" RIGHT="0" SIGNAME="fpga_0_RS232_Uart_1_RX_pin"><DESCRIPTION>Serial Data In</DESCRIPTION></PORT><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="1" MPD_INDEX="43" MSB="0" NAME="TX" RIGHT="0" SIGNAME="fpga_0_RS232_Uart_1_TX_pin"><DESCRIPTION>Serial Data Out</DESCRIPTION></PORT><PORT BUS="SPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="3" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="4" MSB="0" NAME="PLB_masterID" RIGHT="0" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="5" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="6" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="8" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="9" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="10" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="11" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="12" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="13" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="14" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="15" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="16" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="17" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="32" MSB="0" NAME="Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="33" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="34" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="35" MSB="0" NAME="Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="36" MSB="0" NAME="Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="37" MSB="0" NAME="Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="38" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="39" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="40" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT DIR="O" MPD_INDEX="44" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/></PORTS><BUSINTERFACES><BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/></BUSINTERFACES><MEMORYMAP><MEMRANGE BASEDECIMAL="2214592512" BASENAME="C_BASEADDR" BASEVALUE="0x84000000" HIGHDECIMAL="2214658047" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8400ffff" MEMTYPE="REGISTER" MINSIZE="0x10" SIZE="65536" SIZEABRV="64K"><SLAVES><SLAVE BUSINTERFACE="SPLB"/></SLAVES></MEMRANGE></MEMORYMAP></MODULE><MODULE HWVERSION="6.01.a" INSTANCE="DDR3_SDRAM" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="MEMORY_CNTLR" MODTYPE="mpmc"><DESCRIPTION TYPE="SHORT">Multi-Port Memory Controller(DDR/DDR2/SDRAM)</DESCRIPTION><DESCRIPTION TYPE="LONG">Multi-port memory controller.</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="/raid/opt.x86_64/xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v6_01_a/doc/mpmc.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_earlyaccess"/><PARAMETERS><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="virtex6"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_SUBFAMILY" TYPE="STRING" VALUE="lx"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_DEVICE" TYPE="STRING" VALUE="6vlx240t"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_PACKAGE" TYPE="STRING" VALUE="ff1156"/><PARAMETER MPD_INDEX="5" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-1"/><PARAMETER MPD_INDEX="6" NAME="C_SPEEDGRADE_INT" TYPE="INTEGER" VALUE="1"/><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="7" NAME="C_NUM_PORTS" TYPE="INTEGER" VALUE="2"/><PARAMETER MPD_INDEX="8" NAME="C_PORT_CONFIG" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="9" NAME="C_ALL_PIMS_SHARE_ADDRESSES" TYPE="INTEGER" VALUE="1"/><PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="18" MPD_INDEX="10" NAME="C_MPMC_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x90000000"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="11" NAME="C_MPMC_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x9fffffff"/><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="12" NAME="C_MPMC_SW_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="13" NAME="C_MPMC_SW_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="14" NAME="C_SDMA_CTRL_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="15" NAME="C_SDMA_CTRL_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_MPMC_CTRL_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_MPMC_CTRL_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="18" NAME="C_MPMC_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="19" NAME="C_MPMC_CTRL_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="20" NAME="C_MPMC_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="21" NAME="C_MPMC_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="22" NAME="C_MPMC_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="23" NAME="C_MPMC_CTRL_P2P" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="24" NAME="C_MPMC_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="25" NAME="C_MPMC_CTRL_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="26" NAME="C_NUM_IDELAYCTRL" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="27" NAME="C_IDELAYCTRL_LOC" TYPE="STRING" VALUE="NOT_SET"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="28" NAME="C_IODELAY_GRP" TYPE="STRING" VALUE="DDR3_SDRAM"/><PARAMETER MPD_INDEX="29" NAME="C_MCB_LOC" TYPE="STRING" VALUE="NOT_SET"/><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="30" NAME="C_MMCM_EXT_LOC" TYPE="STRING" VALUE="MMCM_ADV_X0Y9"/><PARAMETER MPD_INDEX="31" NAME="C_MMCM_INT_LOC" TYPE="STRING" VALUE="NOT_SET"/><PARAMETER MPD_INDEX="32" NAME="C_MAX_REQ_ALLOWED" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="33" NAME="C_ARB_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="34" NAME="C_WR_DATAPATH_TML_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="35" NAME="C_RD_DATAPATH_TML_MAX_FANOUT" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="36" NAME="C_ARB_USE_DEFAULT" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="37" NAME="C_ARB0_ALGO" TYPE="STRING" VALUE="ROUND_ROBIN"/><PARAMETER MPD_INDEX="38" NAME="C_ARB0_NUM_SLOTS" TYPE="INTEGER" VALUE="8"/><PARAMETER MPD_INDEX="39" NAME="C_ARB0_SLOT0" TYPE="STRING" VALUE="01234567"/><PARAMETER MPD_INDEX="40" NAME="C_ARB0_SLOT1" TYPE="STRING" VALUE="12345670"/><PARAMETER MPD_INDEX="41" NAME="C_ARB0_SLOT2" TYPE="STRING" VALUE="23456701"/><PARAMETER MPD_INDEX="42" NAME="C_ARB0_SLOT3" TYPE="STRING" VALUE="34567012"/><PARAMETER MPD_INDEX="43" NAME="C_ARB0_SLOT4" TYPE="STRING" VALUE="45670123"/><PARAMETER MPD_INDEX="44" NAME="C_ARB0_SLOT5" TYPE="STRING" VALUE="56701234"/><PARAMETER MPD_INDEX="45" NAME="C_ARB0_SLOT6" TYPE="STRING" VALUE="67012345"/><PARAMETER MPD_INDEX="46" NAME="C_ARB0_SLOT7" TYPE="STRING" VALUE="70123456"/><PARAMETER MPD_INDEX="47" NAME="C_ARB0_SLOT8" TYPE="STRING" VALUE="01234567"/><PARAMETER MPD_INDEX="48" NAME="C_ARB0_SLOT9" TYPE="STRING" VALUE="12345670"/><PARAMETER MPD_INDEX="49" NAME="C_ARB0_SLOT10" TYPE="STRING" VALUE="23456701"/><PARAMETER MPD_INDEX="50" NAME="C_ARB0_SLOT11" TYPE="STRING" VALUE="34567012"/><PARAMETER MPD_INDEX="51" NAME="C_ARB0_SLOT12" TYPE="STRING" VALUE="45670123"/><PARAMETER MPD_INDEX="52" NAME="C_ARB0_SLOT13" TYPE="STRING" VALUE="56701234"/><PARAMETER MPD_INDEX="53" NAME="C_ARB0_SLOT14" TYPE="STRING" VALUE="67012345"/><PARAMETER MPD_INDEX="54" NAME="C_ARB0_SLOT15" TYPE="STRING" VALUE="70123456"/><PARAMETER MPD_INDEX="55" NAME="C_PM_ENABLE" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="56" NAME="C_PM_DC_WIDTH" TYPE="INTEGER" VALUE="48"/><PARAMETER MPD_INDEX="57" NAME="C_PM_GC_CNTR" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="58" NAME="C_PM_GC_WIDTH" TYPE="INTEGER" VALUE="48"/><PARAMETER MPD_INDEX="59" NAME="C_PM_SHIFT_CNT_BY" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="60" NAME="C_SKIP_SIM_INIT_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="61" NAME="C_USE_MIG_S3_PHY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="62" NAME="C_USE_MIG_V4_PHY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="63" NAME="C_USE_MIG_V5_PHY" TYPE="INTEGER" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="64" NAME="C_USE_MIG_V6_PHY" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="65" NAME="C_USE_MCB_S6_PHY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="66" NAME="C_USE_STATIC_PHY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="67" NAME="C_STATIC_PHY_RDDATA_CLK_SEL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="68" NAME="C_STATIC_PHY_RDDATA_SWAP_RISE" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="69" NAME="C_STATIC_PHY_RDEN_DELAY" TYPE="INTEGER" VALUE="5"/><PARAMETER MPD_INDEX="70" NAME="C_DEBUG_REG_ENABLE" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="71" NAME="C_SPECIAL_BOARD" TYPE="STRING" VALUE="NONE"/><PARAMETER MPD_INDEX="72" NAME="C_USE_MIG_FLOW" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="73" NAME="C_MEM_ADDR_ORDER" TYPE="STRING" VALUE="BANK_ROW_COLUMN"/><PARAMETER MPD_INDEX="74" NAME="C_MEM_CALIBRATION_MODE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="75" NAME="C_MEM_CALIBRATION_DELAY" TYPE="STRING" VALUE="HALF"/><PARAMETER MPD_INDEX="76" NAME="C_MEM_CALIBRATION_SOFT_IP" TYPE="STRING" VALUE="FALSE"/><PARAMETER MPD_INDEX="77" NAME="C_MEM_CALIBRATION_BYPASS" TYPE="STRING" VALUE="NO"/><PARAMETER MPD_INDEX="78" NAME="C_MPMC_MCB_DRP_CLK_PRESENT" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="79" NAME="C_MEM_SKIP_IN_TERM_CAL" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="80" NAME="C_MEM_SKIP_DYNAMIC_CAL" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="81" NAME="C_MEM_SKIP_DYN_IN_TERM" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="82" NAME="C_MEM_INCDEC_THRESHOLD" TYPE="INTEGER" VALUE="0x02"/><PARAMETER MPD_INDEX="83" NAME="C_MEM_CHECK_MAX_INDELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="84" NAME="C_MEM_CHECK_MAX_TAP_REG" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="85" NAME="C_MEM_TZQINIT_MAXCNT" TYPE="INTEGER" VALUE="512"/><PARAMETER MPD_INDEX="86" NAME="C_MPMC_CLK_MEM_2X_PERIOD_PS" TYPE="INTEGER" VALUE="1250"/><PARAMETER MPD_INDEX="87" NAME="C_MCB_USE_EXTERNAL_BUFPLL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="88" NAME="C_MCB_LDQSP_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="89" NAME="C_MCB_UDQSP_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="90" NAME="C_MCB_LDQSN_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="91" NAME="C_MCB_UDQSN_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="92" NAME="C_MCB_DQ0_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="93" NAME="C_MCB_DQ1_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="94" NAME="C_MCB_DQ2_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="95" NAME="C_MCB_DQ3_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="96" NAME="C_MCB_DQ4_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="97" NAME="C_MCB_DQ5_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="98" NAME="C_MCB_DQ6_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="99" NAME="C_MCB_DQ7_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="100" NAME="C_MCB_DQ8_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="101" NAME="C_MCB_DQ9_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="102" NAME="C_MCB_DQ10_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="103" NAME="C_MCB_DQ11_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="104" NAME="C_MCB_DQ12_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="105" NAME="C_MCB_DQ13_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="106" NAME="C_MCB_DQ14_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="107" NAME="C_MCB_DQ15_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="108" NAME="C_MCB_RZQ_LOC" TYPE="STRING" VALUE="NOT_SET"/><PARAMETER MPD_INDEX="109" NAME="C_MCB_ZIO_LOC" TYPE="STRING" VALUE="NOT_SET"/><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="110" NAME="C_MEM_TYPE" TYPE="STRING" VALUE="DDR3"/><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="111" NAME="C_MEM_PARTNO" TYPE="STRING" VALUE="MT4JSF6464HY-1G1"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="112" NAME="C_MEM_PART_DATA_DEPTH" TYPE="INTEGER" VALUE="64"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="113" NAME="C_MEM_PART_DATA_WIDTH" TYPE="INTEGER" VALUE="16"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="114" NAME="C_MEM_PART_NUM_BANK_BITS" TYPE="INTEGER" VALUE="3"/><PARAMETER MPD_INDEX="115" NAME="C_MEM_PART_NUM_ROW_BITS" TYPE="INTEGER" VALUE="13"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="116" NAME="C_MEM_PART_NUM_COL_BITS" TYPE="INTEGER" VALUE="10"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="117" NAME="C_MEM_PART_TRAS" TYPE="INTEGER" VALUE="37500"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="118" NAME="C_MEM_PART_TRASMAX" TYPE="INTEGER" VALUE="70200000"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="119" NAME="C_MEM_PART_TRC" TYPE="INTEGER" VALUE="50625"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="120" NAME="C_MEM_PART_TRCD" TYPE="INTEGER" VALUE="13130"/><PARAMETER MPD_INDEX="121" NAME="C_MEM_PART_TDQSS" TYPE="INTEGER" VALUE="1"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="122" NAME="C_MEM_PART_TWR" TYPE="INTEGER" VALUE="15000"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="123" NAME="C_MEM_PART_TRP" TYPE="INTEGER" VALUE="13130"/><PARAMETER MPD_INDEX="124" NAME="C_MEM_PART_TMRD" TYPE="INTEGER" VALUE="4"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="125" NAME="C_MEM_PART_TRRD" TYPE="INTEGER" VALUE="7500"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="126" NAME="C_MEM_PART_TRFC" TYPE="INTEGER" VALUE="110000"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="127" NAME="C_MEM_PART_TREFI" TYPE="INTEGER" VALUE="7800000"/><PARAMETER MPD_INDEX="128" NAME="C_MEM_PART_TAL" TYPE="INTEGER" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="129" NAME="C_MEM_PART_TCCD" TYPE="INTEGER" VALUE="4"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="130" NAME="C_MEM_PART_TWTR" TYPE="INTEGER" VALUE="7500"/><PARAMETER MPD_INDEX="131" NAME="C_MEM_PART_TRTP" TYPE="INTEGER" VALUE="7500"/><PARAMETER MPD_INDEX="132" NAME="C_MEM_PART_TZQINIT" TYPE="INTEGER" VALUE="512"/><PARAMETER MPD_INDEX="133" NAME="C_MEM_PART_TZQCS" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="134" NAME="C_MEM_PART_TPRDI" TYPE="INTEGER" VALUE="1000000"/><PARAMETER MPD_INDEX="135" NAME="C_MEM_PART_TZQI" TYPE="INTEGER" VALUE="128000000"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="136" NAME="C_MEM_PART_CAS_A_FMAX" TYPE="INTEGER" VALUE="400.0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="137" NAME="C_MEM_PART_CAS_A" TYPE="INTEGER" VALUE="6"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="138" NAME="C_MEM_PART_CAS_B_FMAX" TYPE="INTEGER" VALUE="533.0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="139" NAME="C_MEM_PART_CAS_B" TYPE="INTEGER" VALUE="7"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="140" NAME="C_MEM_PART_CAS_C_FMAX" TYPE="INTEGER" VALUE="1.0"/><PARAMETER MPD_INDEX="141" NAME="C_MEM_PART_CAS_C" TYPE="INTEGER" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="142" NAME="C_MEM_PART_CAS_D_FMAX" TYPE="INTEGER" VALUE="1.0"/><PARAMETER MPD_INDEX="143" NAME="C_MEM_PART_CAS_D" TYPE="INTEGER" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="144" NAME="C_MPMC_CLK0_PERIOD_PS" TYPE="INTEGER" VALUE="5000"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="145" NAME="C_MPMC_CLK_MEM_PERIOD_PS" TYPE="INTEGER" VALUE="2500"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="146" NAME="C_MEM_CAS_LATENCY" TYPE="INTEGER" VALUE="6"/><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="147" NAME="C_MEM_ODT_TYPE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="148" NAME="C_MEM_REDUCED_DRV" TYPE="INTEGER" VALUE="0"/><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="149" NAME="C_MEM_REG_DIMM" TYPE="INTEGER" VALUE="0"/><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="150" NAME="C_MEM_CLK_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="151" NAME="C_MEM_ODT_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="152" NAME="C_MEM_CE_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="153" NAME="C_MEM_CS_N_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="154" NAME="C_MEM_ADDR_WIDTH" TYPE="INTEGER" VALUE="13"><DESCRIPTION>Address Width</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="155" NAME="C_MEM_BANKADDR_WIDTH" TYPE="INTEGER" VALUE="3"><DESCRIPTION>Bank Address Width</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="156" NAME="C_MEM_DATA_WIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>Data Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="157" NAME="C_MEM_BITS_DATA_PER_DQS" TYPE="INTEGER" VALUE="8"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="158" NAME="C_MEM_DM_WIDTH" TYPE="INTEGER" VALUE="4"><DESCRIPTION>Data Mask Width</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="159" NAME="C_MEM_DQS_WIDTH" TYPE="INTEGER" VALUE="4"><DESCRIPTION>DQS Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="160" NAME="C_MEM_NUM_DIMMS" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="161" NAME="C_MEM_NUM_RANKS" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="162" NAME="C_MEM_DQS_IO_COL" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000000000000000"/><PARAMETER MPD_INDEX="163" NAME="C_MEM_DQ_IO_MS" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000000000000000"/><PARAMETER MPD_INDEX="164" NAME="C_DDR2_DQSN_ENABLE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="165" NAME="C_INCLUDE_ECC_SUPPORT" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="166" NAME="C_ECC_DEFAULT_ON" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="167" NAME="C_INCLUDE_ECC_TEST" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="168" NAME="C_ECC_SEC_THRESHOLD" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="169" NAME="C_ECC_DEC_THRESHOLD" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="170" NAME="C_ECC_PEC_THRESHOLD" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="171" NAME="C_ECC_DATA_WIDTH" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="172" NAME="C_ECC_DM_WIDTH" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="173" NAME="C_ECC_DQS_WIDTH" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="174" NAME="C_MEM_PA_SR" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="175" NAME="C_MEM_CAS_WR_LATENCY" TYPE="INTEGER" VALUE="5"/><PARAMETER MPD_INDEX="176" NAME="C_MEM_AUTO_SR" TYPE="STRING" VALUE="ENABLED"/><PARAMETER MPD_INDEX="177" NAME="C_MEM_HIGH_TEMP_SR" TYPE="STRING" VALUE="NORMAL"/><PARAMETER MPD_INDEX="178" NAME="C_MEM_DYNAMIC_WRITE_ODT" TYPE="STRING" VALUE="OFF"/><PARAMETER MPD_INDEX="179" NAME="C_MEM_WRLVL" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="180" NAME="C_IDELAY_CLK_FREQ" TYPE="STRING" VALUE="DEFAULT"/><PARAMETER MPD_INDEX="181" NAME="C_MEM_PHASE_DETECT" TYPE="STRING" VALUE="DEFAULT"/><PARAMETER MPD_INDEX="182" NAME="C_MEM_IBUF_LPWR_MODE" TYPE="STRING" VALUE="DEFAULT"/><PARAMETER MPD_INDEX="183" NAME="C_MEM_IODELAY_HP_MODE" TYPE="STRING" VALUE="DEFAULT"/><PARAMETER MPD_INDEX="184" NAME="C_MEM_SIM_INIT_OPTION" TYPE="STRING" VALUE="DEFAULT"/><PARAMETER MPD_INDEX="185" NAME="C_MEM_SIM_CAL_OPTION" TYPE="STRING" VALUE="DEFAULT"/><PARAMETER MPD_INDEX="186" NAME="C_MEM_CAL_WIDTH" TYPE="STRING" VALUE="DEFAULT"/><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="187" NAME="C_MEM_NDQS_COL0" TYPE="INTEGER" VALUE="3"/><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="188" NAME="C_MEM_NDQS_COL1" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="189" NAME="C_MEM_NDQS_COL2" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="190" NAME="C_MEM_NDQS_COL3" TYPE="INTEGER" VALUE="0"/><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="191" NAME="C_MEM_DQS_LOC_COL0" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000000000000000000000000000020100"/><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="192" NAME="C_MEM_DQS_LOC_COL1" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000000000000000000000000000000003"/><PARAMETER MPD_INDEX="193" NAME="C_MEM_DQS_LOC_COL2" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000000000000000000000000000000000"/><PARAMETER MPD_INDEX="194" NAME="C_MEM_DQS_LOC_COL3" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000000000000000000000000000000000"/><PARAMETER MPD_INDEX="195" NAME="C_MAINT_PRESCALER_PERIOD" TYPE="INTEGER" VALUE="200000"/><PARAMETER MPD_INDEX="196" NAME="C_TBY4TAPVALUE" TYPE="INTEGER" VALUE="9999"/><PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="197" NAME="C_PIM0_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="198" NAME="C_PIM0_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="199" NAME="C_PIM0_OFFSET" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="200" NAME="C_PIM0_DATA_WIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="201" NAME="C_PIM0_BASETYPE" TYPE="INTEGER" VALUE="2"/><PARAMETER MPD_INDEX="202" NAME="C_PIM0_SUBTYPE" TYPE="STRING" VALUE="PLB"/><PARAMETER MPD_INDEX="203" NAME="C_XCL0_LINESIZE" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="204" NAME="C_XCL0_WRITEXFER" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="205" NAME="C_XCL0_PIPE_STAGES" TYPE="INTEGER" VALUE="2"/><PARAMETER MPD_INDEX="206" NAME="C_XCL0_B_IN_USE" TYPE="INTEGER" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="207" NAME="C_PIM0_B_SUBTYPE" TYPE="STRING" VALUE="PLB"/><PARAMETER MPD_INDEX="208" NAME="C_XCL0_B_LINESIZE" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="209" NAME="C_XCL0_B_WRITEXFER" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="210" NAME="C_SPLB0_AWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="211" NAME="C_SPLB0_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="212" NAME="C_SPLB0_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="213" NAME="C_SPLB0_NUM_MASTERS" TYPE="INTEGER" VALUE="2"/><PARAMETER MPD_INDEX="214" NAME="C_SPLB0_MID_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="215" NAME="C_SPLB0_P2P" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="216" NAME="C_SPLB0_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="217" NAME="C_SPLB0_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="218" NAME="C_SDMA_CTRL0_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="219" NAME="C_SDMA_CTRL0_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="220" NAME="C_SDMA_CTRL0_AWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="221" NAME="C_SDMA_CTRL0_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="222" NAME="C_SDMA_CTRL0_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="223" NAME="C_SDMA_CTRL0_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="224" NAME="C_SDMA_CTRL0_MID_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="225" NAME="C_SDMA_CTRL0_P2P" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="226" NAME="C_SDMA_CTRL0_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="227" NAME="C_SDMA_CTRL0_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="228" NAME="C_SDMA0_COMPLETED_ERR_TX" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="229" NAME="C_SDMA0_COMPLETED_ERR_RX" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="230" NAME="C_SDMA0_PRESCALAR" TYPE="INTEGER" VALUE="1023"/><PARAMETER MPD_INDEX="231" NAME="C_SDMA0_PI2LL_CLK_RATIO" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="232" NAME="C_PPC440MC0_BURST_LENGTH" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="233" NAME="C_PPC440MC0_PIPE_STAGES" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="234" NAME="C_VFBC0_CMD_FIFO_DEPTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="235" NAME="C_VFBC0_CMD_AFULL_COUNT" TYPE="INTEGER" VALUE="3"/><PARAMETER MPD_INDEX="236" NAME="C_VFBC0_RDWD_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="237" NAME="C_VFBC0_RDWD_FIFO_DEPTH" TYPE="INTEGER" VALUE="1024"/><PARAMETER MPD_INDEX="238" NAME="C_VFBC0_RD_AEMPTY_WD_AFULL_COUNT" TYPE="INTEGER" VALUE="3"/><PARAMETER MPD_INDEX="239" NAME="C_PI0_RD_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/><PARAMETER MPD_INDEX="240" NAME="C_PI0_WR_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/><PARAMETER MPD_INDEX="241" NAME="C_PI0_ADDRACK_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="242" NAME="C_PI0_RD_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="243" NAME="C_PI0_RD_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="244" NAME="C_PI0_WR_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="245" NAME="C_PI0_WR_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="246" NAME="C_PI0_PM_USED" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="247" NAME="C_PI0_PM_DC_CNTR" TYPE="INTEGER" VALUE="1"/><PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="248" NAME="C_PIM1_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="249" NAME="C_PIM1_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="250" NAME="C_PIM1_OFFSET" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="251" NAME="C_PIM1_DATA_WIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="252" NAME="C_PIM1_BASETYPE" TYPE="INTEGER" VALUE="4"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="253" NAME="C_PIM1_SUBTYPE" TYPE="STRING" VALUE="NPI"/><PARAMETER MPD_INDEX="254" NAME="C_XCL1_LINESIZE" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="255" NAME="C_XCL1_WRITEXFER" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="256" NAME="C_XCL1_PIPE_STAGES" TYPE="INTEGER" VALUE="2"/><PARAMETER MPD_INDEX="257" NAME="C_XCL1_B_IN_USE" TYPE="INTEGER" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="258" NAME="C_PIM1_B_SUBTYPE" TYPE="STRING" VALUE="NPI"/><PARAMETER MPD_INDEX="259" NAME="C_XCL1_B_LINESIZE" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="260" NAME="C_XCL1_B_WRITEXFER" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="261" NAME="C_SPLB1_AWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="262" NAME="C_SPLB1_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="263" NAME="C_SPLB1_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="264" NAME="C_SPLB1_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="265" NAME="C_SPLB1_MID_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="266" NAME="C_SPLB1_P2P" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="267" NAME="C_SPLB1_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="268" NAME="C_SPLB1_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="269" NAME="C_SDMA_CTRL1_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="270" NAME="C_SDMA_CTRL1_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="271" NAME="C_SDMA_CTRL1_AWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="272" NAME="C_SDMA_CTRL1_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="273" NAME="C_SDMA_CTRL1_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="274" NAME="C_SDMA_CTRL1_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="275" NAME="C_SDMA_CTRL1_MID_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="276" NAME="C_SDMA_CTRL1_P2P" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="277" NAME="C_SDMA_CTRL1_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="278" NAME="C_SDMA_CTRL1_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="279" NAME="C_SDMA1_COMPLETED_ERR_TX" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="280" NAME="C_SDMA1_COMPLETED_ERR_RX" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="281" NAME="C_SDMA1_PRESCALAR" TYPE="INTEGER" VALUE="1023"/><PARAMETER MPD_INDEX="282" NAME="C_SDMA1_PI2LL_CLK_RATIO" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="283" NAME="C_PPC440MC1_BURST_LENGTH" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="284" NAME="C_PPC440MC1_PIPE_STAGES" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="285" NAME="C_VFBC1_CMD_FIFO_DEPTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="286" NAME="C_VFBC1_CMD_AFULL_COUNT" TYPE="INTEGER" VALUE="3"/><PARAMETER MPD_INDEX="287" NAME="C_VFBC1_RDWD_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="288" NAME="C_VFBC1_RDWD_FIFO_DEPTH" TYPE="INTEGER" VALUE="1024"/><PARAMETER MPD_INDEX="289" NAME="C_VFBC1_RD_AEMPTY_WD_AFULL_COUNT" TYPE="INTEGER" VALUE="3"/><PARAMETER MPD_INDEX="290" NAME="C_PI1_RD_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/><PARAMETER MPD_INDEX="291" NAME="C_PI1_WR_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/><PARAMETER MPD_INDEX="292" NAME="C_PI1_ADDRACK_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="293" NAME="C_PI1_RD_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="294" NAME="C_PI1_RD_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="295" NAME="C_PI1_WR_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="296" NAME="C_PI1_WR_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="297" NAME="C_PI1_PM_USED" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="298" NAME="C_PI1_PM_DC_CNTR" TYPE="INTEGER" VALUE="1"/><PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="299" NAME="C_PIM2_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="300" NAME="C_PIM2_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="301" NAME="C_PIM2_OFFSET" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="302" NAME="C_PIM2_DATA_WIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="303" NAME="C_PIM2_BASETYPE" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="304" NAME="C_PIM2_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/><PARAMETER MPD_INDEX="305" NAME="C_XCL2_LINESIZE" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="306" NAME="C_XCL2_WRITEXFER" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="307" NAME="C_XCL2_PIPE_STAGES" TYPE="INTEGER" VALUE="2"/><PARAMETER MPD_INDEX="308" NAME="C_XCL2_B_IN_USE" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="309" NAME="C_PIM2_B_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/><PARAMETER MPD_INDEX="310" NAME="C_XCL2_B_LINESIZE" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="311" NAME="C_XCL2_B_WRITEXFER" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="312" NAME="C_SPLB2_AWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="313" NAME="C_SPLB2_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="314" NAME="C_SPLB2_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="315" NAME="C_SPLB2_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="316" NAME="C_SPLB2_MID_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="317" NAME="C_SPLB2_P2P" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="318" NAME="C_SPLB2_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="319" NAME="C_SPLB2_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="320" NAME="C_SDMA_CTRL2_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="321" NAME="C_SDMA_CTRL2_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="322" NAME="C_SDMA_CTRL2_AWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="323" NAME="C_SDMA_CTRL2_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="324" NAME="C_SDMA_CTRL2_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="325" NAME="C_SDMA_CTRL2_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="326" NAME="C_SDMA_CTRL2_MID_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="327" NAME="C_SDMA_CTRL2_P2P" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="328" NAME="C_SDMA_CTRL2_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="329" NAME="C_SDMA_CTRL2_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="330" NAME="C_SDMA2_COMPLETED_ERR_TX" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="331" NAME="C_SDMA2_COMPLETED_ERR_RX" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="332" NAME="C_SDMA2_PRESCALAR" TYPE="INTEGER" VALUE="1023"/><PARAMETER MPD_INDEX="333" NAME="C_SDMA2_PI2LL_CLK_RATIO" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="334" NAME="C_PPC440MC2_BURST_LENGTH" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="335" NAME="C_PPC440MC2_PIPE_STAGES" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="336" NAME="C_VFBC2_CMD_FIFO_DEPTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="337" NAME="C_VFBC2_CMD_AFULL_COUNT" TYPE="INTEGER" VALUE="3"/><PARAMETER MPD_INDEX="338" NAME="C_VFBC2_RDWD_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="339" NAME="C_VFBC2_RDWD_FIFO_DEPTH" TYPE="INTEGER" VALUE="1024"/><PARAMETER MPD_INDEX="340" NAME="C_VFBC2_RD_AEMPTY_WD_AFULL_COUNT" TYPE="INTEGER" VALUE="3"/><PARAMETER MPD_INDEX="341" NAME="C_PI2_RD_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/><PARAMETER MPD_INDEX="342" NAME="C_PI2_WR_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/><PARAMETER MPD_INDEX="343" NAME="C_PI2_ADDRACK_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="344" NAME="C_PI2_RD_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="345" NAME="C_PI2_RD_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="346" NAME="C_PI2_WR_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="347" NAME="C_PI2_WR_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="348" NAME="C_PI2_PM_USED" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="349" NAME="C_PI2_PM_DC_CNTR" TYPE="INTEGER" VALUE="1"/><PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="350" NAME="C_PIM3_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="351" NAME="C_PIM3_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="352" NAME="C_PIM3_OFFSET" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="353" NAME="C_PIM3_DATA_WIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="354" NAME="C_PIM3_BASETYPE" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="355" NAME="C_PIM3_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/><PARAMETER MPD_INDEX="356" NAME="C_XCL3_LINESIZE" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="357" NAME="C_XCL3_WRITEXFER" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="358" NAME="C_XCL3_PIPE_STAGES" TYPE="INTEGER" VALUE="2"/><PARAMETER MPD_INDEX="359" NAME="C_XCL3_B_IN_USE" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="360" NAME="C_PIM3_B_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/><PARAMETER MPD_INDEX="361" NAME="C_XCL3_B_LINESIZE" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="362" NAME="C_XCL3_B_WRITEXFER" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="363" NAME="C_SPLB3_AWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="364" NAME="C_SPLB3_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="365" NAME="C_SPLB3_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="366" NAME="C_SPLB3_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="367" NAME="C_SPLB3_MID_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="368" NAME="C_SPLB3_P2P" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="369" NAME="C_SPLB3_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="370" NAME="C_SPLB3_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="371" NAME="C_SDMA_CTRL3_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="372" NAME="C_SDMA_CTRL3_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="373" NAME="C_SDMA_CTRL3_AWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="374" NAME="C_SDMA_CTRL3_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="375" NAME="C_SDMA_CTRL3_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="376" NAME="C_SDMA_CTRL3_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="377" NAME="C_SDMA_CTRL3_MID_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="378" NAME="C_SDMA_CTRL3_P2P" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="379" NAME="C_SDMA_CTRL3_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="380" NAME="C_SDMA_CTRL3_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="381" NAME="C_SDMA3_COMPLETED_ERR_TX" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="382" NAME="C_SDMA3_COMPLETED_ERR_RX" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="383" NAME="C_SDMA3_PRESCALAR" TYPE="INTEGER" VALUE="1023"/><PARAMETER MPD_INDEX="384" NAME="C_SDMA3_PI2LL_CLK_RATIO" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="385" NAME="C_PPC440MC3_BURST_LENGTH" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="386" NAME="C_PPC440MC3_PIPE_STAGES" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="387" NAME="C_VFBC3_CMD_FIFO_DEPTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="388" NAME="C_VFBC3_CMD_AFULL_COUNT" TYPE="INTEGER" VALUE="3"/><PARAMETER MPD_INDEX="389" NAME="C_VFBC3_RDWD_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="390" NAME="C_VFBC3_RDWD_FIFO_DEPTH" TYPE="INTEGER" VALUE="1024"/><PARAMETER MPD_INDEX="391" NAME="C_VFBC3_RD_AEMPTY_WD_AFULL_COUNT" TYPE="INTEGER" VALUE="3"/><PARAMETER MPD_INDEX="392" NAME="C_PI3_RD_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/><PARAMETER MPD_INDEX="393" NAME="C_PI3_WR_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/><PARAMETER MPD_INDEX="394" NAME="C_PI3_ADDRACK_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="395" NAME="C_PI3_RD_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="396" NAME="C_PI3_RD_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="397" NAME="C_PI3_WR_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="398" NAME="C_PI3_WR_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="399" NAME="C_PI3_PM_USED" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="400" NAME="C_PI3_PM_DC_CNTR" TYPE="INTEGER" VALUE="1"/><PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="401" NAME="C_PIM4_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="402" NAME="C_PIM4_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="403" NAME="C_PIM4_OFFSET" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="404" NAME="C_PIM4_DATA_WIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="405" NAME="C_PIM4_BASETYPE" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="406" NAME="C_PIM4_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/><PARAMETER MPD_INDEX="407" NAME="C_XCL4_LINESIZE" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="408" NAME="C_XCL4_WRITEXFER" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="409" NAME="C_XCL4_PIPE_STAGES" TYPE="INTEGER" VALUE="2"/><PARAMETER MPD_INDEX="410" NAME="C_XCL4_B_IN_USE" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="411" NAME="C_PIM4_B_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/><PARAMETER MPD_INDEX="412" NAME="C_XCL4_B_LINESIZE" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="413" NAME="C_XCL4_B_WRITEXFER" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="414" NAME="C_SPLB4_AWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="415" NAME="C_SPLB4_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="416" NAME="C_SPLB4_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="417" NAME="C_SPLB4_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="418" NAME="C_SPLB4_MID_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="419" NAME="C_SPLB4_P2P" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="420" NAME="C_SPLB4_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="421" NAME="C_SPLB4_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="422" NAME="C_SDMA_CTRL4_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="423" NAME="C_SDMA_CTRL4_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="424" NAME="C_SDMA_CTRL4_AWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="425" NAME="C_SDMA_CTRL4_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="426" NAME="C_SDMA_CTRL4_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="427" NAME="C_SDMA_CTRL4_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="428" NAME="C_SDMA_CTRL4_MID_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="429" NAME="C_SDMA_CTRL4_P2P" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="430" NAME="C_SDMA_CTRL4_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="431" NAME="C_SDMA_CTRL4_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="432" NAME="C_SDMA4_COMPLETED_ERR_TX" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="433" NAME="C_SDMA4_COMPLETED_ERR_RX" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="434" NAME="C_SDMA4_PRESCALAR" TYPE="INTEGER" VALUE="1023"/><PARAMETER MPD_INDEX="435" NAME="C_SDMA4_PI2LL_CLK_RATIO" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="436" NAME="C_PPC440MC4_BURST_LENGTH" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="437" NAME="C_PPC440MC4_PIPE_STAGES" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="438" NAME="C_VFBC4_CMD_FIFO_DEPTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="439" NAME="C_VFBC4_CMD_AFULL_COUNT" TYPE="INTEGER" VALUE="3"/><PARAMETER MPD_INDEX="440" NAME="C_VFBC4_RDWD_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="441" NAME="C_VFBC4_RDWD_FIFO_DEPTH" TYPE="INTEGER" VALUE="1024"/><PARAMETER MPD_INDEX="442" NAME="C_VFBC4_RD_AEMPTY_WD_AFULL_COUNT" TYPE="INTEGER" VALUE="3"/><PARAMETER MPD_INDEX="443" NAME="C_PI4_RD_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/><PARAMETER MPD_INDEX="444" NAME="C_PI4_WR_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/><PARAMETER MPD_INDEX="445" NAME="C_PI4_ADDRACK_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="446" NAME="C_PI4_RD_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="447" NAME="C_PI4_RD_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="448" NAME="C_PI4_WR_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="449" NAME="C_PI4_WR_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="450" NAME="C_PI4_PM_USED" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="451" NAME="C_PI4_PM_DC_CNTR" TYPE="INTEGER" VALUE="1"/><PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="452" NAME="C_PIM5_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="453" NAME="C_PIM5_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="454" NAME="C_PIM5_OFFSET" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="455" NAME="C_PIM5_DATA_WIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="456" NAME="C_PIM5_BASETYPE" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="457" NAME="C_PIM5_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/><PARAMETER MPD_INDEX="458" NAME="C_XCL5_LINESIZE" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="459" NAME="C_XCL5_WRITEXFER" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="460" NAME="C_XCL5_PIPE_STAGES" TYPE="INTEGER" VALUE="2"/><PARAMETER MPD_INDEX="461" NAME="C_XCL5_B_IN_USE" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="462" NAME="C_PIM5_B_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/><PARAMETER MPD_INDEX="463" NAME="C_XCL5_B_LINESIZE" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="464" NAME="C_XCL5_B_WRITEXFER" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="465" NAME="C_SPLB5_AWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="466" NAME="C_SPLB5_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="467" NAME="C_SPLB5_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="468" NAME="C_SPLB5_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="469" NAME="C_SPLB5_MID_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="470" NAME="C_SPLB5_P2P" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="471" NAME="C_SPLB5_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="472" NAME="C_SPLB5_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="473" NAME="C_SDMA_CTRL5_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="474" NAME="C_SDMA_CTRL5_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="475" NAME="C_SDMA_CTRL5_AWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="476" NAME="C_SDMA_CTRL5_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="477" NAME="C_SDMA_CTRL5_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="478" NAME="C_SDMA_CTRL5_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="479" NAME="C_SDMA_CTRL5_MID_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="480" NAME="C_SDMA_CTRL5_P2P" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="481" NAME="C_SDMA_CTRL5_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="482" NAME="C_SDMA_CTRL5_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="483" NAME="C_SDMA5_COMPLETED_ERR_TX" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="484" NAME="C_SDMA5_COMPLETED_ERR_RX" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="485" NAME="C_SDMA5_PRESCALAR" TYPE="INTEGER" VALUE="1023"/><PARAMETER MPD_INDEX="486" NAME="C_SDMA5_PI2LL_CLK_RATIO" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="487" NAME="C_PPC440MC5_BURST_LENGTH" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="488" NAME="C_PPC440MC5_PIPE_STAGES" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="489" NAME="C_VFBC5_CMD_FIFO_DEPTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="490" NAME="C_VFBC5_CMD_AFULL_COUNT" TYPE="INTEGER" VALUE="3"/><PARAMETER MPD_INDEX="491" NAME="C_VFBC5_RDWD_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="492" NAME="C_VFBC5_RDWD_FIFO_DEPTH" TYPE="INTEGER" VALUE="1024"/><PARAMETER MPD_INDEX="493" NAME="C_VFBC5_RD_AEMPTY_WD_AFULL_COUNT" TYPE="INTEGER" VALUE="3"/><PARAMETER MPD_INDEX="494" NAME="C_PI5_RD_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/><PARAMETER MPD_INDEX="495" NAME="C_PI5_WR_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/><PARAMETER MPD_INDEX="496" NAME="C_PI5_ADDRACK_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="497" NAME="C_PI5_RD_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="498" NAME="C_PI5_RD_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="499" NAME="C_PI5_WR_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="500" NAME="C_PI5_WR_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="501" NAME="C_PI5_PM_USED" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="502" NAME="C_PI5_PM_DC_CNTR" TYPE="INTEGER" VALUE="1"/><PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="503" NAME="C_PIM6_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="504" NAME="C_PIM6_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="505" NAME="C_PIM6_OFFSET" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="506" NAME="C_PIM6_DATA_WIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="507" NAME="C_PIM6_BASETYPE" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="508" NAME="C_PIM6_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/><PARAMETER MPD_INDEX="509" NAME="C_XCL6_LINESIZE" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="510" NAME="C_XCL6_WRITEXFER" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="511" NAME="C_XCL6_PIPE_STAGES" TYPE="INTEGER" VALUE="2"/><PARAMETER MPD_INDEX="512" NAME="C_XCL6_B_IN_USE" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="513" NAME="C_PIM6_B_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/><PARAMETER MPD_INDEX="514" NAME="C_XCL6_B_LINESIZE" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="515" NAME="C_XCL6_B_WRITEXFER" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="516" NAME="C_SPLB6_AWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="517" NAME="C_SPLB6_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="518" NAME="C_SPLB6_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="519" NAME="C_SPLB6_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="520" NAME="C_SPLB6_MID_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="521" NAME="C_SPLB6_P2P" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="522" NAME="C_SPLB6_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="523" NAME="C_SPLB6_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="524" NAME="C_SDMA_CTRL6_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="525" NAME="C_SDMA_CTRL6_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="526" NAME="C_SDMA_CTRL6_AWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="527" NAME="C_SDMA_CTRL6_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="528" NAME="C_SDMA_CTRL6_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="529" NAME="C_SDMA_CTRL6_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="530" NAME="C_SDMA_CTRL6_MID_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="531" NAME="C_SDMA_CTRL6_P2P" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="532" NAME="C_SDMA_CTRL6_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="533" NAME="C_SDMA_CTRL6_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="534" NAME="C_SDMA6_COMPLETED_ERR_TX" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="535" NAME="C_SDMA6_COMPLETED_ERR_RX" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="536" NAME="C_SDMA6_PRESCALAR" TYPE="INTEGER" VALUE="1023"/><PARAMETER MPD_INDEX="537" NAME="C_SDMA6_PI2LL_CLK_RATIO" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="538" NAME="C_PPC440MC6_BURST_LENGTH" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="539" NAME="C_PPC440MC6_PIPE_STAGES" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="540" NAME="C_VFBC6_CMD_FIFO_DEPTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="541" NAME="C_VFBC6_CMD_AFULL_COUNT" TYPE="INTEGER" VALUE="3"/><PARAMETER MPD_INDEX="542" NAME="C_VFBC6_RDWD_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="543" NAME="C_VFBC6_RDWD_FIFO_DEPTH" TYPE="INTEGER" VALUE="1024"/><PARAMETER MPD_INDEX="544" NAME="C_VFBC6_RD_AEMPTY_WD_AFULL_COUNT" TYPE="INTEGER" VALUE="3"/><PARAMETER MPD_INDEX="545" NAME="C_PI6_RD_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/><PARAMETER MPD_INDEX="546" NAME="C_PI6_WR_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/><PARAMETER MPD_INDEX="547" NAME="C_PI6_ADDRACK_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="548" NAME="C_PI6_RD_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="549" NAME="C_PI6_RD_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="550" NAME="C_PI6_WR_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="551" NAME="C_PI6_WR_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="552" NAME="C_PI6_PM_USED" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="553" NAME="C_PI6_PM_DC_CNTR" TYPE="INTEGER" VALUE="1"/><PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="554" NAME="C_PIM7_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="555" NAME="C_PIM7_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="556" NAME="C_PIM7_OFFSET" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="557" NAME="C_PIM7_DATA_WIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="558" NAME="C_PIM7_BASETYPE" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="559" NAME="C_PIM7_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/><PARAMETER MPD_INDEX="560" NAME="C_XCL7_LINESIZE" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="561" NAME="C_XCL7_WRITEXFER" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="562" NAME="C_XCL7_PIPE_STAGES" TYPE="INTEGER" VALUE="2"/><PARAMETER MPD_INDEX="563" NAME="C_XCL7_B_IN_USE" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="564" NAME="C_PIM7_B_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/><PARAMETER MPD_INDEX="565" NAME="C_XCL7_B_LINESIZE" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="566" NAME="C_XCL7_B_WRITEXFER" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="567" NAME="C_SPLB7_AWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="568" NAME="C_SPLB7_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="569" NAME="C_SPLB7_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="570" NAME="C_SPLB7_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="571" NAME="C_SPLB7_MID_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="572" NAME="C_SPLB7_P2P" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="573" NAME="C_SPLB7_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="574" NAME="C_SPLB7_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="575" NAME="C_SDMA_CTRL7_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="576" NAME="C_SDMA_CTRL7_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/><PARAMETER MPD_INDEX="577" NAME="C_SDMA_CTRL7_AWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="578" NAME="C_SDMA_CTRL7_DWIDTH" TYPE="INTEGER" VALUE="64"/><PARAMETER MPD_INDEX="579" NAME="C_SDMA_CTRL7_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="580" NAME="C_SDMA_CTRL7_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="581" NAME="C_SDMA_CTRL7_MID_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="582" NAME="C_SDMA_CTRL7_P2P" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="583" NAME="C_SDMA_CTRL7_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="584" NAME="C_SDMA_CTRL7_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="585" NAME="C_SDMA7_COMPLETED_ERR_TX" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="586" NAME="C_SDMA7_COMPLETED_ERR_RX" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="587" NAME="C_SDMA7_PRESCALAR" TYPE="INTEGER" VALUE="1023"/><PARAMETER MPD_INDEX="588" NAME="C_SDMA7_PI2LL_CLK_RATIO" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="589" NAME="C_PPC440MC7_BURST_LENGTH" TYPE="INTEGER" VALUE="4"/><PARAMETER MPD_INDEX="590" NAME="C_PPC440MC7_PIPE_STAGES" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="591" NAME="C_VFBC7_CMD_FIFO_DEPTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="592" NAME="C_VFBC7_CMD_AFULL_COUNT" TYPE="INTEGER" VALUE="3"/><PARAMETER MPD_INDEX="593" NAME="C_VFBC7_RDWD_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="594" NAME="C_VFBC7_RDWD_FIFO_DEPTH" TYPE="INTEGER" VALUE="1024"/><PARAMETER MPD_INDEX="595" NAME="C_VFBC7_RD_AEMPTY_WD_AFULL_COUNT" TYPE="INTEGER" VALUE="3"/><PARAMETER MPD_INDEX="596" NAME="C_PI7_RD_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/><PARAMETER MPD_INDEX="597" NAME="C_PI7_WR_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/><PARAMETER MPD_INDEX="598" NAME="C_PI7_ADDRACK_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="599" NAME="C_PI7_RD_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="600" NAME="C_PI7_RD_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="601" NAME="C_PI7_WR_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="602" NAME="C_PI7_WR_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="603" NAME="C_PI7_PM_USED" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="604" NAME="C_PI7_PM_DC_CNTR" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="605" NAME="C_WR_TRAINING_PORT" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="606" NAME="C_ARB_BRAM_INIT_00" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111010001000011000000001111111111110010000110100000000011111111111100001101000100000000111111111111011010001000"/><PARAMETER MPD_INDEX="607" NAME="C_ARB_BRAM_INIT_01" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111"/><PARAMETER MPD_INDEX="608" NAME="C_ARB_BRAM_INIT_02" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111011010001000000000001111111111110110100010000000000011111111111101101000100000000000111111111111011010001000"/><PARAMETER MPD_INDEX="609" NAME="C_ARB_BRAM_INIT_03" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111"/><PARAMETER MPD_INDEX="610" NAME="C_ARB_BRAM_INIT_04" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111010001000011000000001111111111110010000110100000000011111111111100001101000100000000111111111111011010001000"/><PARAMETER MPD_INDEX="611" NAME="C_ARB_BRAM_INIT_05" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111"/><PARAMETER MPD_INDEX="612" NAME="C_ARB_BRAM_INIT_06" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111011010001000000000001111111111110110100010000000000011111111111101101000100000000000111111111111011010001000"/><PARAMETER MPD_INDEX="613" NAME="C_ARB_BRAM_INIT_07" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="614" NAME="C_NCK_PER_CLK" TYPE="INTEGER" VALUE="2"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="615" NAME="C_TWR" TYPE="INTEGER" VALUE="15000"/><PARAMETER MPD_INDEX="616" NAME="C_CTRL_COMPLETE_INDEX" TYPE="INTEGER" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="617" NAME="C_CTRL_IS_WRITE_INDEX" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="618" NAME="C_CTRL_PHYIF_RAS_N_INDEX" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="619" NAME="C_CTRL_PHYIF_CAS_N_INDEX" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="620" NAME="C_CTRL_PHYIF_WE_N_INDEX" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="621" NAME="C_CTRL_RMW_INDEX" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="622" NAME="C_CTRL_SKIP_0_INDEX" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="623" NAME="C_CTRL_PHYIF_DQS_O_INDEX" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="624" NAME="C_CTRL_SKIP_1_INDEX" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="625" NAME="C_CTRL_DP_RDFIFO_PUSH_INDEX" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="626" NAME="C_CTRL_SKIP_2_INDEX" TYPE="INTEGER" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="627" NAME="C_CTRL_AP_COL_CNT_LOAD_INDEX" TYPE="INTEGER" VALUE="12"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="628" NAME="C_CTRL_AP_COL_CNT_ENABLE_INDEX" TYPE="INTEGER" VALUE="13"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="629" NAME="C_CTRL_AP_PRECHARGE_ADDR10_INDEX" TYPE="INTEGER" VALUE="14"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="630" NAME="C_CTRL_AP_ROW_COL_SEL_INDEX" TYPE="INTEGER" VALUE="15"/><PARAMETER MPD_INDEX="631" NAME="C_CTRL_PHYIF_FORCE_DM_INDEX" TYPE="INTEGER" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="632" NAME="C_CTRL_REPEAT4_INDEX" TYPE="INTEGER" VALUE="17"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="633" NAME="C_CTRL_DFI_RAS_N_0_INDEX" TYPE="INTEGER" VALUE="2"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="634" NAME="C_CTRL_DFI_CAS_N_0_INDEX" TYPE="INTEGER" VALUE="3"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="635" NAME="C_CTRL_DFI_WE_N_0_INDEX" TYPE="INTEGER" VALUE="4"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="636" NAME="C_CTRL_DFI_RAS_N_1_INDEX" TYPE="INTEGER" VALUE="20"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="637" NAME="C_CTRL_DFI_CAS_N_1_INDEX" TYPE="INTEGER" VALUE="21"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="638" NAME="C_CTRL_DFI_WE_N_1_INDEX" TYPE="INTEGER" VALUE="22"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="639" NAME="C_CTRL_DP_WRFIFO_POP_INDEX" TYPE="INTEGER" VALUE="8"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="640" NAME="C_CTRL_DFI_WRDATA_EN_INDEX" TYPE="INTEGER" VALUE="18"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="641" NAME="C_CTRL_DFI_RDDATA_EN_INDEX" TYPE="INTEGER" VALUE="19"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="642" NAME="C_CTRL_AP_OTF_ADDR12_INDEX" TYPE="INTEGER" VALUE="23"/><PARAMETER MPD_INDEX="643" NAME="C_CTRL_ARB_RDMODWR_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="644" NAME="C_CTRL_AP_COL_DELAY" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="645" NAME="C_CTRL_AP_PI_ADDR_CE_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="646" NAME="C_CTRL_AP_PORT_SELECT_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="647" NAME="C_CTRL_AP_PIPELINE1_CE_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="648" NAME="C_CTRL_DP_LOAD_RDWDADDR_DELAY" TYPE="INTEGER" VALUE="2"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="649" NAME="C_CTRL_DP_RDFIFO_WHICHPORT_DELAY" TYPE="INTEGER" VALUE="15"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="650" NAME="C_CTRL_DP_SIZE_DELAY" TYPE="INTEGER" VALUE="2"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="651" NAME="C_CTRL_DP_WRFIFO_WHICHPORT_DELAY" TYPE="INTEGER" VALUE="1"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="652" NAME="C_CTRL_PHYIF_DUMMYREADSTART_DELAY" TYPE="INTEGER" VALUE="5"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="653" NAME="C_CTRL_Q0_DELAY" TYPE="INTEGER" VALUE="1"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="654" NAME="C_CTRL_Q1_DELAY" TYPE="INTEGER" VALUE="1"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="655" NAME="C_CTRL_Q2_DELAY" TYPE="INTEGER" VALUE="2"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="656" NAME="C_CTRL_Q3_DELAY" TYPE="INTEGER" VALUE="2"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="657" NAME="C_CTRL_Q4_DELAY" TYPE="INTEGER" VALUE="2"/><PARAMETER MPD_INDEX="658" NAME="C_CTRL_Q5_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="659" NAME="C_CTRL_Q6_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="660" NAME="C_CTRL_Q7_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="661" NAME="C_CTRL_Q8_DELAY" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="662" NAME="C_CTRL_Q9_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="663" NAME="C_CTRL_Q10_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="664" NAME="C_CTRL_Q11_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="665" NAME="C_CTRL_Q12_DELAY" TYPE="INTEGER" VALUE="1"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="666" NAME="C_CTRL_Q13_DELAY" TYPE="INTEGER" VALUE="1"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="667" NAME="C_CTRL_Q14_DELAY" TYPE="INTEGER" VALUE="1"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="668" NAME="C_CTRL_Q15_DELAY" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="669" NAME="C_CTRL_Q16_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="670" NAME="C_CTRL_Q17_DELAY" TYPE="INTEGER" VALUE="1"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="671" NAME="C_CTRL_Q18_DELAY" TYPE="INTEGER" VALUE="2"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="672" NAME="C_CTRL_Q19_DELAY" TYPE="INTEGER" VALUE="2"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="673" NAME="C_CTRL_Q20_DELAY" TYPE="INTEGER" VALUE="2"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="674" NAME="C_CTRL_Q21_DELAY" TYPE="INTEGER" VALUE="2"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="675" NAME="C_CTRL_Q22_DELAY" TYPE="INTEGER" VALUE="2"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="676" NAME="C_CTRL_Q23_DELAY" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="677" NAME="C_CTRL_Q24_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="678" NAME="C_CTRL_Q25_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="679" NAME="C_CTRL_Q26_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="680" NAME="C_CTRL_Q27_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="681" NAME="C_CTRL_Q28_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="682" NAME="C_CTRL_Q29_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="683" NAME="C_CTRL_Q30_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="684" NAME="C_CTRL_Q31_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="685" NAME="C_CTRL_Q32_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="686" NAME="C_CTRL_Q33_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="687" NAME="C_CTRL_Q34_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="688" NAME="C_CTRL_Q35_DELAY" TYPE="INTEGER" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="689" NAME="C_SKIP_1_VALUE" TYPE="INTEGER" VALUE="0x001"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="690" NAME="C_SKIP_2_VALUE" TYPE="INTEGER" VALUE="0x001"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="691" NAME="C_SKIP_3_VALUE" TYPE="INTEGER" VALUE="0x001"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="692" NAME="C_SKIP_4_VALUE" TYPE="INTEGER" VALUE="0x001"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="693" NAME="C_SKIP_5_VALUE" TYPE="INTEGER" VALUE="0x001"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="694" NAME="C_SKIP_6_VALUE" TYPE="INTEGER" VALUE="0x001"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="695" NAME="C_SKIP_7_VALUE" TYPE="INTEGER" VALUE="0x001"/><PARAMETER MPD_INDEX="696" NAME="C_B16_REPEAT_CNT" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="697" NAME="C_B32_REPEAT_CNT" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="698" NAME="C_B64_REPEAT_CNT" TYPE="INTEGER" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="699" NAME="C_ZQCS_REPEAT_CNT" TYPE="INTEGER" VALUE="6"/><PARAMETER MPD_INDEX="700" NAME="C_BASEADDR_CTRL0" TYPE="STD_LOGIC_VECTOR" VALUE="0x000"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="701" NAME="C_HIGHADDR_CTRL0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00f"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="702" NAME="C_BASEADDR_CTRL1" TYPE="STD_LOGIC_VECTOR" VALUE="0x010"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="703" NAME="C_HIGHADDR_CTRL1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01b"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="704" NAME="C_BASEADDR_CTRL2" TYPE="STD_LOGIC_VECTOR" VALUE="0x01c"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="705" NAME="C_HIGHADDR_CTRL2" TYPE="STD_LOGIC_VECTOR" VALUE="0x02b"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="706" NAME="C_BASEADDR_CTRL3" TYPE="STD_LOGIC_VECTOR" VALUE="0x02c"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="707" NAME="C_HIGHADDR_CTRL3" TYPE="STD_LOGIC_VECTOR" VALUE="0x037"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="708" NAME="C_BASEADDR_CTRL4" TYPE="STD_LOGIC_VECTOR" VALUE="0x038"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="709" NAME="C_HIGHADDR_CTRL4" TYPE="STD_LOGIC_VECTOR" VALUE="0x047"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="710" NAME="C_BASEADDR_CTRL5" TYPE="STD_LOGIC_VECTOR" VALUE="0x048"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="711" NAME="C_HIGHADDR_CTRL5" TYPE="STD_LOGIC_VECTOR" VALUE="0x053"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="712" NAME="C_BASEADDR_CTRL6" TYPE="STD_LOGIC_VECTOR" VALUE="0x054"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="713" NAME="C_HIGHADDR_CTRL6" TYPE="STD_LOGIC_VECTOR" VALUE="0x063"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="714" NAME="C_BASEADDR_CTRL7" TYPE="STD_LOGIC_VECTOR" VALUE="0x064"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="715" NAME="C_HIGHADDR_CTRL7" TYPE="STD_LOGIC_VECTOR" VALUE="0x06f"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="716" NAME="C_BASEADDR_CTRL8" TYPE="STD_LOGIC_VECTOR" VALUE="0x070"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="717" NAME="C_HIGHADDR_CTRL8" TYPE="STD_LOGIC_VECTOR" VALUE="0x081"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="718" NAME="C_BASEADDR_CTRL9" TYPE="STD_LOGIC_VECTOR" VALUE="0x082"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="719" NAME="C_HIGHADDR_CTRL9" TYPE="STD_LOGIC_VECTOR" VALUE="0x08e"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="720" NAME="C_BASEADDR_CTRL10" TYPE="STD_LOGIC_VECTOR" VALUE="0x08f"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="721" NAME="C_HIGHADDR_CTRL10" TYPE="STD_LOGIC_VECTOR" VALUE="0x0a4"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="722" NAME="C_BASEADDR_CTRL11" TYPE="STD_LOGIC_VECTOR" VALUE="0x0a5"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="723" NAME="C_HIGHADDR_CTRL11" TYPE="STD_LOGIC_VECTOR" VALUE="0x0b5"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="724" NAME="C_BASEADDR_CTRL12" TYPE="STD_LOGIC_VECTOR" VALUE="0x0b6"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="725" NAME="C_HIGHADDR_CTRL12" TYPE="STD_LOGIC_VECTOR" VALUE="0x0d3"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="726" NAME="C_BASEADDR_CTRL13" TYPE="STD_LOGIC_VECTOR" VALUE="0x0d4"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="727" NAME="C_HIGHADDR_CTRL13" TYPE="STD_LOGIC_VECTOR" VALUE="0x0ec"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="728" NAME="C_BASEADDR_CTRL14" TYPE="STD_LOGIC_VECTOR" VALUE="0x0ed"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="729" NAME="C_HIGHADDR_CTRL14" TYPE="STD_LOGIC_VECTOR" VALUE="0x106"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="730" NAME="C_BASEADDR_CTRL15" TYPE="STD_LOGIC_VECTOR" VALUE="0x107"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="731" NAME="C_HIGHADDR_CTRL15" TYPE="STD_LOGIC_VECTOR" VALUE="0x107"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="732" NAME="C_BASEADDR_CTRL16" TYPE="STD_LOGIC_VECTOR" VALUE="0x108"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="733" NAME="C_HIGHADDR_CTRL16" TYPE="STD_LOGIC_VECTOR" VALUE="0x110"/><PARAMETER MPD_INDEX="734" NAME="C_CTRL_BRAM_INIT_3F" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="735" NAME="C_CTRL_BRAM_INIT_3E" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="736" NAME="C_CTRL_BRAM_INIT_3D" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="737" NAME="C_CTRL_BRAM_INIT_3C" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="738" NAME="C_CTRL_BRAM_INIT_3B" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="739" NAME="C_CTRL_BRAM_INIT_3A" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="740" NAME="C_CTRL_BRAM_INIT_39" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="741" NAME="C_CTRL_BRAM_INIT_38" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="742" NAME="C_CTRL_BRAM_INIT_37" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="743" NAME="C_CTRL_BRAM_INIT_36" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="744" NAME="C_CTRL_BRAM_INIT_35" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="745" NAME="C_CTRL_BRAM_INIT_34" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="746" NAME="C_CTRL_BRAM_INIT_33" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="747" NAME="C_CTRL_BRAM_INIT_32" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="748" NAME="C_CTRL_BRAM_INIT_31" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="749" NAME="C_CTRL_BRAM_INIT_30" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="750" NAME="C_CTRL_BRAM_INIT_2F" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="751" NAME="C_CTRL_BRAM_INIT_2E" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="752" NAME="C_CTRL_BRAM_INIT_2D" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="753" NAME="C_CTRL_BRAM_INIT_2C" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="754" NAME="C_CTRL_BRAM_INIT_2B" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="755" NAME="C_CTRL_BRAM_INIT_2A" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="756" NAME="C_CTRL_BRAM_INIT_29" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="757" NAME="C_CTRL_BRAM_INIT_28" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="758" NAME="C_CTRL_BRAM_INIT_27" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="759" NAME="C_CTRL_BRAM_INIT_26" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="760" NAME="C_CTRL_BRAM_INIT_25" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="761" NAME="C_CTRL_BRAM_INIT_24" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER MPD_INDEX="762" NAME="C_CTRL_BRAM_INIT_23" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="763" NAME="C_CTRL_BRAM_INIT_22" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC0070001C"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="764" NAME="C_CTRL_BRAM_INIT_21" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001C0070001C0070001C0070001C0070001D0070001C0072001C0070000C"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="765" NAME="C_CTRL_BRAM_INIT_20" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001C0070001C0070001C0070001C0070001C0070001C0070001D0070001C"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="766" NAME="C_CTRL_BRAM_INIT_1F" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001C0070001C0070001C0070001C0070001C0070001C0070001C0070001C"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="767" NAME="C_CTRL_BRAM_INIT_1E" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001C0070001C0070001C0070001C0070001C0070001C0070001C0040001C"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="768" NAME="C_CTRL_BRAM_INIT_1D" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001C0070001C007040080070001C0070001C0070001C0070001C0020401C"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="769" NAME="C_CTRL_BRAM_INIT_1C" TYPE="STD_LOGIC_VECTOR" VALUE="0x0078001D00D8201C0078001C00D8201C0078001C00D8201C0078001C00D8201C"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="770" NAME="C_CTRL_BRAM_INIT_1B" TYPE="STD_LOGIC_VECTOR" VALUE="0x0078001C00D8201C0078001C00D8201C0078001C00D8201C0078001C00D8201C"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="771" NAME="C_CTRL_BRAM_INIT_1A" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070101C0070001C007080180070001C0070001E0070001E0070001E0070400A"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="772" NAME="C_CTRL_BRAM_INIT_19" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001E0070001F0070001E0070001E0070001E0070201E0074001E0094201E"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="773" NAME="C_CTRL_BRAM_INIT_18" TYPE="STD_LOGIC_VECTOR" VALUE="0x0074011E0094211E0074011E0094211E0074011E0094211E0074011E0094211E"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="774" NAME="C_CTRL_BRAM_INIT_17" TYPE="STD_LOGIC_VECTOR" VALUE="0x0074011E0094211E0074011E0094211E0074011E0094211E0070111E0070011E"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="775" NAME="C_CTRL_BRAM_INIT_16" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070801A0070001E0070001C0070001C0070001C0070001C0020401C0078001D"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="776" NAME="C_CTRL_BRAM_INIT_15" TYPE="STD_LOGIC_VECTOR" VALUE="0x00D8201C0078001C00D8201C0078001C00D8201C0078001C00D8201C0070101C"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="777" NAME="C_CTRL_BRAM_INIT_14" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001C007080180070001C0070001E0070001E0070001E0070400A0070001E"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="778" NAME="C_CTRL_BRAM_INIT_13" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001F0070001E0070001E0070001E0070201E0074001E0094201E0074011E"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="779" NAME="C_CTRL_BRAM_INIT_12" TYPE="STD_LOGIC_VECTOR" VALUE="0x0094211E0074011E0094211E0074011E0094211E0070111E0070011E0070801A"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="780" NAME="C_CTRL_BRAM_INIT_11" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001E0070001C0070001C0070001C0070001C0020401C0078001D00D8201C"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="781" NAME="C_CTRL_BRAM_INIT_10" TYPE="STD_LOGIC_VECTOR" VALUE="0x0078001C00D8201C0070101C0070001C007080180070001C0070001E0070001E"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="782" NAME="C_CTRL_BRAM_INIT_0F" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001E0070400A0070001E0070001F0070001E0070001E0070001E0070201E"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="783" NAME="C_CTRL_BRAM_INIT_0E" TYPE="STD_LOGIC_VECTOR" VALUE="0x0074001E0094201E0074011E0094211E0070111E0070011E0070801A0070001E"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="784" NAME="C_CTRL_BRAM_INIT_0D" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001C0070001C0070001C0020401C0070001C0070001D0078001C00D8201C"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="785" NAME="C_CTRL_BRAM_INIT_0C" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070101C0070001C007080180070001C0070001E0070001E0070001E0070400A"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="786" NAME="C_CTRL_BRAM_INIT_0B" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001E0070001F0070001E0070001E0070001E0070201E0074001E0094201E"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="787" NAME="C_CTRL_BRAM_INIT_0A" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070111E0070011E0070801A0070001E0070001C0070001C0070001C0020401C"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="788" NAME="C_CTRL_BRAM_INIT_09" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001C0070001D0070001C0058201C0070101C0070001C007080180070001C"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="789" NAME="C_CTRL_BRAM_INIT_08" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001E0070001E0070001E0070400A0070001E0070001F0070001E0070001E"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="790" NAME="C_CTRL_BRAM_INIT_07" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001E0070001E0070201E0014201E0070101E0070011E0070801A0070001E"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="791" NAME="C_CTRL_BRAM_INIT_06" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001C0070001C0070001C0020401C0070001C0070001D0070001C0058201C"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="792" NAME="C_CTRL_BRAM_INIT_05" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070101C0070001C007080180070001C0070001E0070001E0070001E0070400A"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="793" NAME="C_CTRL_BRAM_INIT_04" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001E0070001F0070001E0070001E0070001E0070001E0070001E0014201E"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="794" NAME="C_CTRL_BRAM_INIT_03" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070101E0070011E0070801A0070001E0070001C0070001C0070001C0020401C"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="795" NAME="C_CTRL_BRAM_INIT_02" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001C0070001D0070001C0058201C0070101C0070001C007080180070001C"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="796" NAME="C_CTRL_BRAM_INIT_01" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001E0070001E0070001E0070400A0070001E0070001F0070001E0070001E"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="797" NAME="C_CTRL_BRAM_INIT_00" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001E0070001E0070001E0014201E0070101E0070011E0070801A0070001E"/><PARAMETER MPD_INDEX="798" NAME="C_CTRL_BRAM_SRVAL" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000002FC"/><PARAMETER MPD_INDEX="799" NAME="C_CTRL_BRAM_INITP_07" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000"/><PARAMETER MPD_INDEX="800" NAME="C_CTRL_BRAM_INITP_06" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000"/><PARAMETER MPD_INDEX="801" NAME="C_CTRL_BRAM_INITP_05" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000"/><PARAMETER MPD_INDEX="802" NAME="C_CTRL_BRAM_INITP_04" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="803" NAME="C_CTRL_BRAM_INITP_03" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="804" NAME="C_CTRL_BRAM_INITP_02" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="805" NAME="C_CTRL_BRAM_INITP_01" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="806" NAME="C_CTRL_BRAM_INITP_00" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000"/></PARAMETERS><PORTS><PORT CLKFREQUENCY="200000000" DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="1674" MSB="0" NAME="MPMC_Clk0" RIGHT="0" SIGIS="CLK" SIGNAME="clk_200_0000MHzMMCM0"/><PORT CLKFREQUENCY="200000000" DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="1" MPD_INDEX="1677" MSB="0" NAME="MPMC_Clk_200MHz" RIGHT="0" SIGIS="CLK" SIGNAME="clk_200_0000MHzMMCM0"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="2" MPD_INDEX="1678" MSB="0" NAME="MPMC_Rst" RIGHT="0" SIGIS="RST" SIGNAME="sys_periph_reset"/><PORT CLKFREQUENCY="400000000" DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="3" MPD_INDEX="1679" MSB="0" NAME="MPMC_Clk_Mem" RIGHT="0" SIGIS="CLK" SIGNAME="clk_400_0000MHzMMCM0"/><PORT CLKFREQUENCY="400000000" DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="4" MPD_INDEX="1684" MSB="0" NAME="MPMC_Clk_Rd_Base" RIGHT="0" SIGIS="CLK" SIGNAME="clk_400_0000MHzMMCM0_nobuf_varphase"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="5" MPD_INDEX="1695" MSB="0" NAME="MPMC_DCM_PSEN" RIGHT="0" SIGNAME="MPMC_DCM_PSEN"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="6" MPD_INDEX="1696" MSB="0" NAME="MPMC_DCM_PSINCDEC" RIGHT="0" SIGNAME="MPMC_DCM_PSINCDEC"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="7" MPD_INDEX="1697" MSB="0" NAME="MPMC_DCM_PSDONE" RIGHT="0" SIGNAME="MPMC_DCM_PSDONE"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="8" MPD_INDEX="1739" MSB="0" NAME="DDR3_Clk" RIGHT="0" SIGIS="CLK" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_Clk_pin" VECFORMULA="[C_MEM_CLK_WIDTH-1:0]"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="9" MPD_INDEX="1740" MSB="0" NAME="DDR3_Clk_n" RIGHT="0" SIGIS="CLK" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin" VECFORMULA="[C_MEM_CLK_WIDTH-1:0]"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="10" MPD_INDEX="1741" MSB="0" NAME="DDR3_CE" RIGHT="0" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_CE_pin" VECFORMULA="[C_MEM_CE_WIDTH-1:0]"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="11" MPD_INDEX="1742" MSB="0" NAME="DDR3_CS_n" RIGHT="0" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_CS_n_pin" VECFORMULA="[C_MEM_CS_N_WIDTH-1:0]"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="12" MPD_INDEX="1743" MSB="0" NAME="DDR3_ODT" RIGHT="0" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_ODT_pin" VECFORMULA="[C_MEM_ODT_WIDTH-1:0]"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="13" MPD_INDEX="1744" MSB="0" NAME="DDR3_RAS_n" RIGHT="0" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="14" MPD_INDEX="1745" MSB="0" NAME="DDR3_CAS_n" RIGHT="0" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="15" MPD_INDEX="1746" MSB="0" NAME="DDR3_WE_n" RIGHT="0" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_WE_n_pin"/><PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="16" MPD_INDEX="1747" MSB="2" NAME="DDR3_BankAddr" RIGHT="0" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin" VECFORMULA="[C_MEM_BANKADDR_WIDTH-1:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="12" LSB="0" MHS_INDEX="17" MPD_INDEX="1748" MSB="12" NAME="DDR3_Addr" RIGHT="0" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_Addr_pin" VECFORMULA="[C_MEM_ADDR_WIDTH-1:0]"/><PORT DIR="IO" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="31" LSB="0" MHS_INDEX="18" MPD_INDEX="1749" MSB="31" NAME="DDR3_DQ" RIGHT="0" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_DQ_pin" VECFORMULA="[C_ECC_DATA_WIDTH + C_MEM_DATA_WIDTH-1:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="19" MPD_INDEX="1750" MSB="3" NAME="DDR3_DM" RIGHT="0" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_DM_pin" VECFORMULA="[C_ECC_DM_WIDTH + C_MEM_DM_WIDTH-1:0]"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="20" MPD_INDEX="1751" MSB="0" NAME="DDR3_Reset_n" RIGHT="0" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin"/><PORT DIR="IO" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="3" LSB="0" MHS_INDEX="21" MPD_INDEX="1752" MSB="3" NAME="DDR3_DQS" RIGHT="0" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_DQS_pin" VECFORMULA="[C_ECC_DQS_WIDTH + C_MEM_DQS_WIDTH-1:0]"/><PORT DIR="IO" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="3" LSB="0" MHS_INDEX="22" MPD_INDEX="1753" MSB="3" NAME="DDR3_DQS_n" RIGHT="0" SIGNAME="fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin" VECFORMULA="[C_ECC_DQS_WIDTH + C_MEM_DQS_WIDTH-1:0]"/><PORT BUS="XCL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="FSL0_M_Clk" SIGIS="CLK" SIGNAME="__NOC__"/><PORT BUS="XCL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1" NAME="FSL0_M_Write" SIGNAME="__NOC__"/><PORT BUS="XCL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="FSL0_M_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/><PORT BUS="XCL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="3" NAME="FSL0_M_Control" SIGNAME="__NOC__"/><PORT BUS="XCL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="4" NAME="FSL0_M_Full" SIGNAME="__NOC__"/><PORT BUS="XCL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="FSL0_S_Clk" SIGNAME="__NOC__"/><PORT BUS="XCL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="6" NAME="FSL0_S_Read" SIGNAME="__NOC__"/><PORT BUS="XCL0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="FSL0_S_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/><PORT BUS="XCL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="8" NAME="FSL0_S_Control" SIGNAME="__NOC__"/><PORT BUS="XCL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="9" NAME="FSL0_S_Exists" SIGNAME="__NOC__"/><PORT BUS="XCL0_B" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="10" NAME="FSL0_B_M_Clk" SIGIS="CLK" SIGNAME="__NOC__"/><PORT BUS="XCL0_B" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="11" NAME="FSL0_B_M_Write" SIGNAME="__NOC__"/><PORT BUS="XCL0_B" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="FSL0_B_M_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/><PORT BUS="XCL0_B" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="13" NAME="FSL0_B_M_Control" SIGNAME="__NOC__"/><PORT BUS="XCL0_B" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="FSL0_B_M_Full" SIGNAME="__NOC__"/><PORT BUS="XCL0_B" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="15" NAME="FSL0_B_S_Clk" SIGNAME="__NOC__"/><PORT BUS="XCL0_B" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="16" NAME="FSL0_B_S_Read" SIGNAME="__NOC__"/><PORT BUS="XCL0_B" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="FSL0_B_S_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/><PORT BUS="XCL0_B" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="18" NAME="FSL0_B_S_Control" SIGNAME="__NOC__"/><PORT BUS="XCL0_B" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="19" NAME="FSL0_B_S_Exists" SIGNAME="__NOC__"/><PORT BUS="SPLB0" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="20" NAME="SPLB0_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="21" NAME="SPLB0_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="22" MSB="0" NAME="SPLB0_PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="23" NAME="SPLB0_PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="24" NAME="SPLB0_PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="25" MSB="0" NAME="SPLB0_PLB_masterID" RIGHT="0" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB0_MID_WIDTH-1)]"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="26" NAME="SPLB0_PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="27" MSB="0" NAME="SPLB0_PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB0_DWIDTH/8)-1)]"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB0_PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="29" NAME="SPLB0_PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="30" NAME="SPLB0_PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="31" NAME="SPLB0_PLB_abort" SIGNAME="mb_plb_PLB_abort"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="32" NAME="SPLB0_PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="33" MSB="0" NAME="SPLB0_PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="SPLB0_PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="35" MSB="0" NAME="SPLB0_PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="36" NAME="SPLB0_PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="37" NAME="SPLB0_PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="38" MSB="0" NAME="SPLB0_PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="39" NAME="SPLB0_PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="40" MSB="0" NAME="SPLB0_PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="41" MSB="0" NAME="SPLB0_PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="42" MSB="0" NAME="SPLB0_PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="43" NAME="SPLB0_PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="44" NAME="SPLB0_PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="45" MSB="0" NAME="SPLB0_PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB0_DWIDTH-1)]"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="46" NAME="SPLB0_Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB0_Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="48" NAME="SPLB0_Sl_wait" SIGNAME="mb_plb_Sl_wait"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="49" NAME="SPLB0_Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="50" NAME="SPLB0_Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="51" NAME="SPLB0_Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="52" NAME="SPLB0_Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="53" MSB="0" NAME="SPLB0_Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB0_DWIDTH-1)]"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="54" MSB="0" NAME="SPLB0_Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="55" NAME="SPLB0_Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="56" NAME="SPLB0_Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="57" NAME="SPLB0_Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="58" MSB="0" NAME="SPLB0_Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB0_NUM_MASTERS-1)]"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="59" MSB="0" NAME="SPLB0_Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB0_NUM_MASTERS-1)]"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="60" MSB="0" NAME="SPLB0_Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB0_NUM_MASTERS-1)]"/><PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="61" MSB="0" NAME="SPLB0_Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB0_NUM_MASTERS-1)]"/><PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="SDMA0_Clk" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="63" NAME="SDMA0_Rx_IntOut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="64" NAME="SDMA0_Tx_IntOut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/><PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="SDMA0_RstOut" SIGNAME="__NOC__"/><PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="66" MSB="0" NAME="SDMA0_TX_D" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/><PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="67" MSB="0" NAME="SDMA0_TX_Rem" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/><PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="68" NAME="SDMA0_TX_SOF" SIGNAME="__NOC__"/><PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="SDMA0_TX_EOF" SIGNAME="__NOC__"/><PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="70" NAME="SDMA0_TX_SOP" SIGNAME="__NOC__"/><PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="SDMA0_TX_EOP" SIGNAME="__NOC__"/><PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="72" NAME="SDMA0_TX_Src_Rdy" SIGNAME="__NOC__"/><PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="73" NAME="SDMA0_TX_Dst_Rdy" SIGNAME="__NOC__"/><PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="74" MSB="0" NAME="SDMA0_RX_D" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/><PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="75" MSB="0" NAME="SDMA0_RX_Rem" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/><PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="76" NAME="SDMA0_RX_SOF" SIGNAME="__NOC__"/><PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="77" NAME="SDMA0_RX_EOF" SIGNAME="__NOC__"/><PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="78" NAME="SDMA0_RX_SOP" SIGNAME="__NOC__"/><PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="SDMA0_RX_EOP" SIGNAME="__NOC__"/><PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="80" NAME="SDMA0_RX_Src_Rdy" SIGNAME="__NOC__"/><PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="81" NAME="SDMA0_RX_Dst_Rdy" SIGNAME="__NOC__"/><PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="82" NAME="SDMA_CTRL0_Clk" SIGIS="CLK" SIGNAME="__NOC__"/><PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="83" NAME="SDMA_CTRL0_Rst" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" 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DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="302" NAME="SDMA_CTRL1_PLB_lockErr" SIGNAME="__NOC__"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="303" NAME="SDMA_CTRL1_PLB_wrPendReq" SIGNAME="__NOC__"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="304" MSB="0" NAME="SDMA_CTRL1_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="305" NAME="SDMA_CTRL1_PLB_rdPendReq" SIGNAME="__NOC__"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="306" MSB="0" NAME="SDMA_CTRL1_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="307" MSB="0" NAME="SDMA_CTRL1_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="308" MSB="0" NAME="SDMA_CTRL1_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="309" NAME="SDMA_CTRL1_PLB_rdBurst" SIGNAME="__NOC__"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="310" NAME="SDMA_CTRL1_PLB_wrBurst" SIGNAME="__NOC__"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="311" MSB="0" NAME="SDMA_CTRL1_PLB_wrDBus" RIGHT="63" SIGNAME="__NOC__" VECFORMULA="[0:(C_SDMA_CTRL1_DWIDTH-1)]"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="312" NAME="SDMA_CTRL1_Sl_addrAck" SIGNAME="__NOC__"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="313" MSB="0" NAME="SDMA_CTRL1_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="314" NAME="SDMA_CTRL1_Sl_wait" SIGNAME="__NOC__"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="315" NAME="SDMA_CTRL1_Sl_rearbitrate" SIGNAME="__NOC__"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="316" NAME="SDMA_CTRL1_Sl_wrDAck" SIGNAME="__NOC__"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="317" NAME="SDMA_CTRL1_Sl_wrComp" SIGNAME="__NOC__"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="318" NAME="SDMA_CTRL1_Sl_wrBTerm" SIGNAME="__NOC__"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="319" MSB="0" NAME="SDMA_CTRL1_Sl_rdDBus" RIGHT="63" SIGNAME="__NOC__" VECFORMULA="[0:(C_SDMA_CTRL1_DWIDTH-1)]"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="320" MSB="0" NAME="SDMA_CTRL1_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="321" NAME="SDMA_CTRL1_Sl_rdDAck" SIGNAME="__NOC__"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="322" NAME="SDMA_CTRL1_Sl_rdComp" SIGNAME="__NOC__"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="323" NAME="SDMA_CTRL1_Sl_rdBTerm" SIGNAME="__NOC__"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="324" MSB="0" NAME="SDMA_CTRL1_Sl_MBusy" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[0:(C_SDMA_CTRL1_NUM_MASTERS-1)]"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="325" MSB="0" NAME="SDMA_CTRL1_Sl_MRdErr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[0:(C_SDMA_CTRL1_NUM_MASTERS-1)]"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="326" MSB="0" NAME="SDMA_CTRL1_Sl_MWrErr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[0:(C_SDMA_CTRL1_NUM_MASTERS-1)]"/><PORT BUS="SDMA_CTRL1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="327" MSB="0" NAME="SDMA_CTRL1_Sl_MIRQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[0:(C_SDMA_CTRL1_NUM_MASTERS-1)]"/><PORT BUS="MPMC_PIM1" DEF_SIGNAME="npi_complete_0_XIL_NPI_Addr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="328" MSB="31" NAME="PIM1_Addr" RIGHT="0" SIGNAME="npi_complete_0_XIL_NPI_Addr" VECFORMULA="[31:0]"/><PORT BUS="MPMC_PIM1" DEF_SIGNAME="npi_complete_0_XIL_NPI_AddrReq" DIR="I" MPD_INDEX="329" NAME="PIM1_AddrReq" SIGNAME="npi_complete_0_XIL_NPI_AddrReq"/><PORT BUS="MPMC_PIM1" DEF_SIGNAME="npi_complete_0_XIL_NPI_AddrAck" DIR="O" MPD_INDEX="330" NAME="PIM1_AddrAck" SIGNAME="npi_complete_0_XIL_NPI_AddrAck"/><PORT BUS="MPMC_PIM1" DEF_SIGNAME="npi_complete_0_XIL_NPI_RNW" DIR="I" MPD_INDEX="331" NAME="PIM1_RNW" SIGNAME="npi_complete_0_XIL_NPI_RNW"/><PORT BUS="MPMC_PIM1" DEF_SIGNAME="npi_complete_0_XIL_NPI_Size" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="332" MSB="3" NAME="PIM1_Size" RIGHT="0" SIGNAME="npi_complete_0_XIL_NPI_Size" VECFORMULA="[3:0]"/><PORT BUS="MPMC_PIM1" DEF_SIGNAME="npi_complete_0_XIL_NPI_RdModWr" DIR="I" MPD_INDEX="333" NAME="PIM1_RdModWr" SIGNAME="npi_complete_0_XIL_NPI_RdModWr"/><PORT BUS="MPMC_PIM1" DEF_SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_Data" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="334" MSB="63" NAME="PIM1_WrFIFO_Data" RIGHT="0" SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_Data" VECFORMULA="[(C_PIM1_DATA_WIDTH-1):0]"/><PORT BUS="MPMC_PIM1" DEF_SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_BE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="335" MSB="7" NAME="PIM1_WrFIFO_BE" RIGHT="0" SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_BE" VECFORMULA="[(C_PIM1_DATA_WIDTH/8-1):0]"/><PORT BUS="MPMC_PIM1" DEF_SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_Push" DIR="I" MPD_INDEX="336" NAME="PIM1_WrFIFO_Push" SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_Push"/><PORT BUS="MPMC_PIM1" DEF_SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_Data" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="337" MSB="63" NAME="PIM1_RdFIFO_Data" RIGHT="0" SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_Data" VECFORMULA="[(C_PIM1_DATA_WIDTH-1):0]"/><PORT BUS="MPMC_PIM1" DEF_SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_Pop" DIR="I" MPD_INDEX="338" NAME="PIM1_RdFIFO_Pop" SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_Pop"/><PORT BUS="MPMC_PIM1" DEF_SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_RdWdAddr" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="339" MSB="3" NAME="PIM1_RdFIFO_RdWdAddr" RIGHT="0" SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_RdWdAddr" VECFORMULA="[3:0]"/><PORT BUS="MPMC_PIM1" DEF_SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_Empty" DIR="O" MPD_INDEX="340" NAME="PIM1_WrFIFO_Empty" SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_Empty"/><PORT BUS="MPMC_PIM1" DEF_SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_AlmostFull" DIR="O" MPD_INDEX="341" NAME="PIM1_WrFIFO_AlmostFull" SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_AlmostFull"/><PORT BUS="MPMC_PIM1" DEF_SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_Flush" DIR="I" MPD_INDEX="342" NAME="PIM1_WrFIFO_Flush" SIGNAME="npi_complete_0_XIL_NPI_WrFIFO_Flush"/><PORT BUS="MPMC_PIM1" DEF_SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_Empty" DIR="O" MPD_INDEX="343" NAME="PIM1_RdFIFO_Empty" SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_Empty"/><PORT BUS="MPMC_PIM1" DEF_SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_Flush" DIR="I" MPD_INDEX="344" NAME="PIM1_RdFIFO_Flush" SIGNAME="npi_complete_0_XIL_NPI_RdFIFO_Flush"/><PORT BUS="MPMC_PIM1" DEF_SIGNAME="npi_complete_0_XIL_NPI_RDFIFO_Latency" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="345" MSB="1" NAME="PIM1_RdFIFO_Latency" RIGHT="0" SIGNAME="npi_complete_0_XIL_NPI_RDFIFO_Latency" VECFORMULA="[1:0]"/><PORT BUS="MPMC_PIM1" DEF_SIGNAME="npi_complete_0_XIL_NPI_InitDone" DIR="O" MPD_INDEX="346" NAME="PIM1_InitDone" SIGNAME="npi_complete_0_XIL_NPI_InitDone"/><PORT BUS="PPC440MC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="347" NAME="PPC440MC1_MIMCReadNotWrite" SIGNAME="__NOC__"/><PORT BUS="PPC440MC1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="35" MPD_INDEX="348" MSB="0" NAME="PPC440MC1_MIMCAddress" RIGHT="35" SIGNAME="__NOC__" VECFORMULA="[0:35]"/><PORT BUS="PPC440MC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="349" NAME="PPC440MC1_MIMCAddressValid" SIGNAME="__NOC__"/><PORT BUS="PPC440MC1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="127" MPD_INDEX="350" MSB="0" NAME="PPC440MC1_MIMCWriteData" RIGHT="127" SIGNAME="__NOC__" VECFORMULA="[0:127]"/><PORT BUS="PPC440MC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="351" NAME="PPC440MC1_MIMCWriteDataValid" SIGNAME="__NOC__"/><PORT BUS="PPC440MC1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="352" MSB="0" NAME="PPC440MC1_MIMCByteEnable" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/><PORT BUS="PPC440MC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="353" NAME="PPC440MC1_MIMCBankConflict" SIGNAME="__NOC__"/><PORT BUS="PPC440MC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="354" NAME="PPC440MC1_MIMCRowConflict" SIGNAME="__NOC__"/><PORT BUS="PPC440MC1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="127" MPD_INDEX="355" MSB="0" NAME="PPC440MC1_MCMIReadData" RIGHT="127" SIGNAME="__NOC__" VECFORMULA="[0:127]"/><PORT BUS="PPC440MC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="356" NAME="PPC440MC1_MCMIReadDataValid" SIGNAME="__NOC__"/><PORT BUS="PPC440MC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="357" NAME="PPC440MC1_MCMIReadDataErr" SIGNAME="__NOC__"/><PORT BUS="PPC440MC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="358" NAME="PPC440MC1_MCMIAddrReadyToAccept" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="359" NAME="VFBC1_Cmd_Clk" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="360" NAME="VFBC1_Cmd_Reset" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="361" MSB="31" NAME="VFBC1_Cmd_Data" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="362" NAME="VFBC1_Cmd_Write" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="363" NAME="VFBC1_Cmd_End" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="364" NAME="VFBC1_Cmd_Full" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="365" NAME="VFBC1_Cmd_Almost_Full" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="366" NAME="VFBC1_Cmd_Idle" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="367" NAME="VFBC1_Wd_Clk" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="368" NAME="VFBC1_Wd_Reset" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="369" NAME="VFBC1_Wd_Write" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="370" NAME="VFBC1_Wd_End_Burst" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="371" NAME="VFBC1_Wd_Flush" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="372" MSB="31" NAME="VFBC1_Wd_Data" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_VFBC1_RDWD_DATA_WIDTH-1:0]"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="373" MSB="3" NAME="VFBC1_Wd_Data_BE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_VFBC1_RDWD_DATA_WIDTH/8-1:0]"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="374" NAME="VFBC1_Wd_Full" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="375" NAME="VFBC1_Wd_Almost_Full" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="376" NAME="VFBC1_Rd_Clk" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="377" NAME="VFBC1_Rd_Reset" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="378" NAME="VFBC1_Rd_Read" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="379" NAME="VFBC1_Rd_End_Burst" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="380" NAME="VFBC1_Rd_Flush" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="381" MSB="31" NAME="VFBC1_Rd_Data" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_VFBC1_RDWD_DATA_WIDTH-1:0]"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="382" NAME="VFBC1_Rd_Empty" SIGNAME="__NOC__"/><PORT BUS="VFBC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="383" NAME="VFBC1_Rd_Almost_Empty" SIGNAME="__NOC__"/><PORT BUS="MCB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="384" NAME="MCB1_cmd_clk" SIGNAME="__NOC__"/><PORT BUS="MCB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="385" NAME="MCB1_cmd_en" SIGNAME="__NOC__"/><PORT BUS="MCB1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="386" MSB="2" NAME="MCB1_cmd_instr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/><PORT BUS="MCB1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="387" MSB="5" NAME="MCB1_cmd_bl" RIGHT="0" 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MPD_INDEX="1587" NAME="VFBC7_Cmd_End" SIGNAME="__NOC__"/><PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1588" NAME="VFBC7_Cmd_Full" SIGNAME="__NOC__"/><PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1589" NAME="VFBC7_Cmd_Almost_Full" SIGNAME="__NOC__"/><PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1590" NAME="VFBC7_Cmd_Idle" SIGNAME="__NOC__"/><PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1591" NAME="VFBC7_Wd_Clk" SIGNAME="__NOC__"/><PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1592" NAME="VFBC7_Wd_Reset" SIGNAME="__NOC__"/><PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1593" NAME="VFBC7_Wd_Write" SIGNAME="__NOC__"/><PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1594" NAME="VFBC7_Wd_End_Burst" SIGNAME="__NOC__"/><PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1595" NAME="VFBC7_Wd_Flush" SIGNAME="__NOC__"/><PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="1596" MSB="31" NAME="VFBC7_Wd_Data" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_VFBC7_RDWD_DATA_WIDTH-1:0]"/><PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="1597" MSB="3" NAME="VFBC7_Wd_Data_BE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_VFBC7_RDWD_DATA_WIDTH/8-1:0]"/><PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1598" NAME="VFBC7_Wd_Full" SIGNAME="__NOC__"/><PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1599" NAME="VFBC7_Wd_Almost_Full" SIGNAME="__NOC__"/><PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1600" NAME="VFBC7_Rd_Clk" SIGNAME="__NOC__"/><PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1601" NAME="VFBC7_Rd_Reset" SIGNAME="__NOC__"/><PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1602" NAME="VFBC7_Rd_Read" SIGNAME="__NOC__"/><PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1603" NAME="VFBC7_Rd_End_Burst" SIGNAME="__NOC__"/><PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1604" NAME="VFBC7_Rd_Flush" SIGNAME="__NOC__"/><PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="1605" MSB="31" NAME="VFBC7_Rd_Data" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_VFBC7_RDWD_DATA_WIDTH-1:0]"/><PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1606" NAME="VFBC7_Rd_Empty" SIGNAME="__NOC__"/><PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1607" NAME="VFBC7_Rd_Almost_Empty" SIGNAME="__NOC__"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1608" NAME="MCB7_cmd_clk" SIGNAME="__NOC__"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1609" NAME="MCB7_cmd_en" SIGNAME="__NOC__"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="1610" MSB="2" NAME="MCB7_cmd_instr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="1611" MSB="5" NAME="MCB7_cmd_bl" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[5:0]"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="29" LSB="0" MPD_INDEX="1612" MSB="29" NAME="MCB7_cmd_byte_addr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[29:0]"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1613" NAME="MCB7_cmd_empty" SIGNAME="__NOC__"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1614" NAME="MCB7_cmd_full" SIGNAME="__NOC__"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1615" NAME="MCB7_wr_clk" SIGNAME="__NOC__"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1616" NAME="MCB7_wr_en" SIGNAME="__NOC__"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="1617" MSB="7" NAME="MCB7_wr_mask" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_PIM7_DATA_WIDTH/8-1:0]"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="1618" MSB="63" NAME="MCB7_wr_data" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_PIM7_DATA_WIDTH-1:0]"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1619" NAME="MCB7_wr_full" SIGNAME="__NOC__"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1620" NAME="MCB7_wr_empty" SIGNAME="__NOC__"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="1621" MSB="6" NAME="MCB7_wr_count" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[6:0]"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1622" NAME="MCB7_wr_underrun" SIGNAME="__NOC__"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1623" NAME="MCB7_wr_error" SIGNAME="__NOC__"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1624" NAME="MCB7_rd_clk" SIGNAME="__NOC__"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1625" NAME="MCB7_rd_en" SIGNAME="__NOC__"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="1626" MSB="63" NAME="MCB7_rd_data" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_PIM7_DATA_WIDTH-1:0]"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1627" NAME="MCB7_rd_full" SIGNAME="__NOC__"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1628" NAME="MCB7_rd_empty" SIGNAME="__NOC__"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="1629" MSB="6" NAME="MCB7_rd_count" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[6:0]"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1630" NAME="MCB7_rd_overflow" SIGNAME="__NOC__"/><PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1631" NAME="MCB7_rd_error" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1632" NAME="MPMC_CTRL_Clk" SIGIS="CLK" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1633" NAME="MPMC_CTRL_Rst" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="1634" MSB="0" NAME="MPMC_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1635" NAME="MPMC_CTRL_PLB_PAValid" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1636" NAME="MPMC_CTRL_PLB_SAValid" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="1637" MSB="0" NAME="MPMC_CTRL_PLB_masterID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[0:(C_MPMC_CTRL_MID_WIDTH-1)]"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1638" NAME="MPMC_CTRL_PLB_RNW" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="1639" MSB="0" NAME="MPMC_CTRL_PLB_BE" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:((C_MPMC_CTRL_DWIDTH/8)-1)]"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="1640" MSB="0" NAME="MPMC_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1641" NAME="MPMC_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1642" NAME="MPMC_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1643" NAME="MPMC_CTRL_PLB_abort" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1644" NAME="MPMC_CTRL_PLB_busLock" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="1645" MSB="0" NAME="MPMC_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="1646" MSB="0" NAME="MPMC_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="1647" MSB="0" NAME="MPMC_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1648" NAME="MPMC_CTRL_PLB_lockErr" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1649" NAME="MPMC_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="1650" MSB="0" NAME="MPMC_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1651" NAME="MPMC_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="1652" MSB="0" NAME="MPMC_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="1653" MSB="0" NAME="MPMC_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="1654" MSB="0" NAME="MPMC_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1655" NAME="MPMC_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1656" NAME="MPMC_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="1657" MSB="0" NAME="MPMC_CTRL_PLB_wrDBus" RIGHT="63" SIGNAME="__NOC__" VECFORMULA="[0:(C_MPMC_CTRL_DWIDTH-1)]"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1658" NAME="MPMC_CTRL_Sl_addrAck" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="1659" MSB="0" NAME="MPMC_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1660" NAME="MPMC_CTRL_Sl_wait" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1661" NAME="MPMC_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1662" NAME="MPMC_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1663" NAME="MPMC_CTRL_Sl_wrComp" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1664" NAME="MPMC_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="1665" MSB="0" NAME="MPMC_CTRL_Sl_rdDBus" RIGHT="63" SIGNAME="__NOC__" VECFORMULA="[0:(C_MPMC_CTRL_DWIDTH-1)]"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="1666" MSB="0" NAME="MPMC_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1667" NAME="MPMC_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1668" NAME="MPMC_CTRL_Sl_rdComp" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1669" NAME="MPMC_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="1670" MSB="0" NAME="MPMC_CTRL_Sl_MBusy" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[0:(C_MPMC_CTRL_NUM_MASTERS-1)]"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="1671" MSB="0" NAME="MPMC_CTRL_Sl_MRdErr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[0:(C_MPMC_CTRL_NUM_MASTERS-1)]"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="1672" MSB="0" NAME="MPMC_CTRL_Sl_MWrErr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[0:(C_MPMC_CTRL_NUM_MASTERS-1)]"/><PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="1673" MSB="0" NAME="MPMC_CTRL_Sl_MIRQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[0:(C_MPMC_CTRL_NUM_MASTERS-1)]"/><PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="1675" NAME="MPMC_Clk0_DIV2" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="1676" NAME="MPMC_Clk90" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="1680" NAME="MPMC_Clk_Mem_2x" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="1681" NAME="MPMC_Clk_Mem_2x_180" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="1682" NAME="MPMC_Clk_Mem_2x_CE0" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="1683" NAME="MPMC_Clk_Mem_2x_CE90" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="1685" NAME="MPMC_Clk_Mem_2x_bufpll_o" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="1686" NAME="MPMC_Clk_Mem_2x_180_bufpll_o" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="1687" NAME="MPMC_Clk_Mem_2x_CE0_bufpll_o" SIGIS="CLK" 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IS_VALID="FALSE" LEFT="0" LSB="0" MPD_INDEX="1700" MSB="0" NAME="SDRAM_CE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_MEM_CE_WIDTH-1:0]"/><PORT DIR="O" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="0" MPD_INDEX="1701" MSB="0" NAME="SDRAM_CS_n" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_MEM_CS_N_WIDTH-1:0]"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="1702" NAME="SDRAM_RAS_n" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="1703" NAME="SDRAM_CAS_n" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="1704" NAME="SDRAM_WE_n" SIGNAME="__NOC__"/><PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="1705" MSB="2" NAME="SDRAM_BankAddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_MEM_BANKADDR_WIDTH-1:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="12" LSB="0" MPD_INDEX="1706" MSB="12" NAME="SDRAM_Addr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_MEM_ADDR_WIDTH-1:0]"/><PORT DIR="IO" ENDIAN="LITTLE" IS_THREE_STATE="FALSE" IS_VALID="FALSE" LEFT="31" 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BUSSTD_PSF="XIL_LL_DMA" IS_VALID="FALSE" MPD_INDEX="49" NAME="SDMA_LL5" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_NPI" IS_VALID="FALSE" MPD_INDEX="50" NAME="MPMC_PIM5" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_PPC440MC" IS_VALID="FALSE" MPD_INDEX="51" NAME="PPC440MC5" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_VFBC" IS_VALID="FALSE" MPD_INDEX="52" NAME="VFBC5" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MCB_PORT" IS_VALID="FALSE" MPD_INDEX="53" NAME="MCB5" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="54" NAME="XCL6" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="55" NAME="XCL6_B" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="56" NAME="SPLB6" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="57" NAME="SDMA_CTRL6" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_LL_DMA" IS_VALID="FALSE" MPD_INDEX="58" NAME="SDMA_LL6" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_NPI" IS_VALID="FALSE" MPD_INDEX="59" NAME="MPMC_PIM6" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_PPC440MC" IS_VALID="FALSE" MPD_INDEX="60" NAME="PPC440MC6" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_VFBC" IS_VALID="FALSE" MPD_INDEX="61" NAME="VFBC6" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MCB_PORT" IS_VALID="FALSE" MPD_INDEX="62" NAME="MCB6" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="63" NAME="XCL7" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="64" NAME="XCL7_B" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="65" NAME="SPLB7" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="66" NAME="SDMA_CTRL7" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_LL_DMA" IS_VALID="FALSE" MPD_INDEX="67" NAME="SDMA_LL7" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_NPI" IS_VALID="FALSE" MPD_INDEX="68" NAME="MPMC_PIM7" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_PPC440MC" IS_VALID="FALSE" MPD_INDEX="69" NAME="PPC440MC7" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_VFBC" IS_VALID="FALSE" MPD_INDEX="70" NAME="VFBC7" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MCB_PORT" IS_VALID="FALSE" MPD_INDEX="71" NAME="MCB7" TYPE="TARGET"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="72" NAME="MPMC_CTRL" TYPE="SLAVE"/></BUSINTERFACES><MEMORYMAP><MEMRANGE BASEDECIMAL="2415919104" BASENAME="C_MPMC_BASEADDR" BASEVALUE="0x90000000" HIGHDECIMAL="2684354559" HIGHNAME="C_MPMC_HIGHADDR" HIGHVALUE="0x9fffffff" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="268435456" SIZEABRV="256M"><SLAVES><SLAVE BUSINTERFACE="XCL0"/><SLAVE BUSINTERFACE="XCL0_B"/><SLAVE BUSINTERFACE="SPLB0"/><SLAVE BUSINTERFACE="SDMA_LL0"/><SLAVE BUSINTERFACE="PPC440MC0"/><SLAVE BUSINTERFACE="VFBC0"/><SLAVE BUSINTERFACE="XCL1"/><SLAVE BUSINTERFACE="XCL1_B"/><SLAVE BUSINTERFACE="SPLB1"/><SLAVE BUSINTERFACE="SDMA_LL1"/><SLAVE BUSINTERFACE="PPC440MC1"/><SLAVE BUSINTERFACE="VFBC1"/><SLAVE BUSINTERFACE="XCL2"/><SLAVE BUSINTERFACE="XCL2_B"/><SLAVE BUSINTERFACE="SPLB2"/><SLAVE BUSINTERFACE="SDMA_LL2"/><SLAVE BUSINTERFACE="PPC440MC2"/><SLAVE BUSINTERFACE="VFBC2"/><SLAVE BUSINTERFACE="XCL3"/><SLAVE BUSINTERFACE="XCL3_B"/><SLAVE BUSINTERFACE="SPLB3"/><SLAVE BUSINTERFACE="SDMA_LL3"/><SLAVE BUSINTERFACE="PPC440MC3"/><SLAVE BUSINTERFACE="VFBC3"/><SLAVE BUSINTERFACE="XCL4"/><SLAVE BUSINTERFACE="XCL4_B"/><SLAVE BUSINTERFACE="SPLB4"/><SLAVE BUSINTERFACE="SDMA_LL4"/><SLAVE BUSINTERFACE="PPC440MC4"/><SLAVE BUSINTERFACE="VFBC4"/><SLAVE BUSINTERFACE="XCL5"/><SLAVE BUSINTERFACE="XCL5_B"/><SLAVE BUSINTERFACE="SPLB5"/><SLAVE BUSINTERFACE="SDMA_LL5"/><SLAVE BUSINTERFACE="PPC440MC5"/><SLAVE BUSINTERFACE="VFBC5"/><SLAVE BUSINTERFACE="XCL6"/><SLAVE BUSINTERFACE="XCL6_B"/><SLAVE BUSINTERFACE="SPLB6"/><SLAVE BUSINTERFACE="SDMA_LL6"/><SLAVE BUSINTERFACE="PPC440MC6"/><SLAVE BUSINTERFACE="VFBC6"/><SLAVE BUSINTERFACE="XCL7"/><SLAVE BUSINTERFACE="XCL7_B"/><SLAVE BUSINTERFACE="SPLB7"/><SLAVE BUSINTERFACE="SDMA_LL7"/><SLAVE BUSINTERFACE="PPC440MC7"/><SLAVE BUSINTERFACE="VFBC7"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_MPMC_SW_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_MPMC_SW_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U"/><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SDMA_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SDMA_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="SDMA_CTRL0"/><SLAVE BUSINTERFACE="SDMA_CTRL1"/><SLAVE BUSINTERFACE="SDMA_CTRL2"/><SLAVE BUSINTERFACE="SDMA_CTRL3"/><SLAVE BUSINTERFACE="SDMA_CTRL4"/><SLAVE BUSINTERFACE="SDMA_CTRL5"/><SLAVE BUSINTERFACE="SDMA_CTRL6"/><SLAVE BUSINTERFACE="SDMA_CTRL7"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_MPMC_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_MPMC_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="MPMC_CTRL"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_PIM0_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_PIM0_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="XCL0"/><SLAVE BUSINTERFACE="XCL0_B"/><SLAVE BUSINTERFACE="SPLB0"/><SLAVE BUSINTERFACE="SDMA_LL0"/><SLAVE BUSINTERFACE="PPC440MC0"/><SLAVE BUSINTERFACE="VFBC0"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SDMA_CTRL0_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SDMA_CTRL0_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="SDMA_CTRL0"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_PIM1_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_PIM1_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="XCL1"/><SLAVE BUSINTERFACE="XCL1_B"/><SLAVE BUSINTERFACE="SPLB1"/><SLAVE BUSINTERFACE="SDMA_LL1"/><SLAVE BUSINTERFACE="PPC440MC1"/><SLAVE BUSINTERFACE="VFBC1"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SDMA_CTRL1_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SDMA_CTRL1_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="SDMA_CTRL1"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_PIM2_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_PIM2_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="XCL2"/><SLAVE BUSINTERFACE="XCL2_B"/><SLAVE BUSINTERFACE="SPLB2"/><SLAVE BUSINTERFACE="SDMA_LL2"/><SLAVE BUSINTERFACE="PPC440MC2"/><SLAVE BUSINTERFACE="VFBC2"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SDMA_CTRL2_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SDMA_CTRL2_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="SDMA_CTRL2"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_PIM3_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_PIM3_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="XCL3"/><SLAVE BUSINTERFACE="XCL3_B"/><SLAVE BUSINTERFACE="SPLB3"/><SLAVE BUSINTERFACE="SDMA_LL3"/><SLAVE BUSINTERFACE="PPC440MC3"/><SLAVE BUSINTERFACE="VFBC3"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SDMA_CTRL3_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SDMA_CTRL3_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="SDMA_CTRL3"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_PIM4_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_PIM4_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="XCL4"/><SLAVE BUSINTERFACE="XCL4_B"/><SLAVE BUSINTERFACE="SPLB4"/><SLAVE BUSINTERFACE="SDMA_LL4"/><SLAVE BUSINTERFACE="PPC440MC4"/><SLAVE BUSINTERFACE="VFBC4"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SDMA_CTRL4_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SDMA_CTRL4_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="SDMA_CTRL4"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_PIM5_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_PIM5_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="XCL5"/><SLAVE BUSINTERFACE="XCL5_B"/><SLAVE BUSINTERFACE="SPLB5"/><SLAVE BUSINTERFACE="SDMA_LL5"/><SLAVE BUSINTERFACE="PPC440MC5"/><SLAVE BUSINTERFACE="VFBC5"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SDMA_CTRL5_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SDMA_CTRL5_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="SDMA_CTRL5"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_PIM6_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_PIM6_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="XCL6"/><SLAVE BUSINTERFACE="XCL6_B"/><SLAVE BUSINTERFACE="SPLB6"/><SLAVE BUSINTERFACE="SDMA_LL6"/><SLAVE BUSINTERFACE="PPC440MC6"/><SLAVE BUSINTERFACE="VFBC6"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SDMA_CTRL6_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SDMA_CTRL6_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="SDMA_CTRL6"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_PIM7_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_PIM7_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="XCL7"/><SLAVE BUSINTERFACE="XCL7_B"/><SLAVE BUSINTERFACE="SPLB7"/><SLAVE BUSINTERFACE="SDMA_LL7"/><SLAVE BUSINTERFACE="PPC440MC7"/><SLAVE BUSINTERFACE="VFBC7"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SDMA_CTRL7_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SDMA_CTRL7_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="SDMA_CTRL7"/></SLAVES></MEMRANGE></MEMORYMAP></MODULE><MODULE HWVERSION="4.00.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="IP" MODTYPE="clock_generator"><DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION><DESCRIPTION TYPE="LONG">Clock generator for processor system.</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="/raid/opt.x86_64/xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/clock_generator_v4_00_a/doc/clock_generator.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6"><DESCRIPTION>Family</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="6vlx240t"><DESCRIPTION>Device</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PACKAGE" TYPE="STRING" VALUE="ff1156"><DESCRIPTION>Package</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-1"><DESCRIPTION>Speed Grade</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="4" NAME="C_CLKIN_FREQ" TYPE="INTEGER" VALUE="200000000"><DESCRIPTION>Input Clock Frequency (Hz) </DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_CLKOUT0_FREQ" TYPE="INTEGER" VALUE="100000000"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_CLKOUT0_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase </DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="7" NAME="C_CLKOUT0_GROUP" TYPE="STRING" VALUE="MMCM0"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="8" NAME="C_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="9" NAME="C_CLKOUT0_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="10" NAME="C_CLKOUT1_FREQ" TYPE="INTEGER" VALUE="200000000"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="11" NAME="C_CLKOUT1_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="12" NAME="C_CLKOUT1_GROUP" TYPE="STRING" VALUE="MMCM0"><DESCRIPTION>Required Group </DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="13" NAME="C_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="14" NAME="C_CLKOUT1_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="15" NAME="C_CLKOUT2_FREQ" TYPE="INTEGER" VALUE="400000000"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="16" NAME="C_CLKOUT2_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="17" NAME="C_CLKOUT2_GROUP" TYPE="STRING" VALUE="MMCM0"><DESCRIPTION>Required Group </DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="18" NAME="C_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="19" NAME="C_CLKOUT2_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Varaible Phase</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="20" NAME="C_CLKOUT3_FREQ" TYPE="INTEGER" VALUE="400000000"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="21" NAME="C_CLKOUT3_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="22" NAME="C_CLKOUT3_GROUP" TYPE="STRING" VALUE="MMCM0"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="23" NAME="C_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="18" MPD_INDEX="24" NAME="C_CLKOUT3_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="25" NAME="C_CLKOUT4_FREQ" TYPE="INTEGER" VALUE="150000000"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="26" NAME="C_CLKOUT4_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="27" NAME="C_CLKOUT4_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group </DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="28" NAME="C_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="29" NAME="C_CLKOUT4_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="30" NAME="C_CLKOUT5_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="31" NAME="C_CLKOUT5_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="32" NAME="C_CLKOUT5_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="33" NAME="C_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="34" NAME="C_CLKOUT5_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="35" NAME="C_CLKOUT6_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="36" NAME="C_CLKOUT6_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="37" NAME="C_CLKOUT6_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="38" NAME="C_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="39" NAME="C_CLKOUT6_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="40" NAME="C_CLKOUT7_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="41" NAME="C_CLKOUT7_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="42" NAME="C_CLKOUT7_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="43" NAME="C_CLKOUT7_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="44" NAME="C_CLKOUT7_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="45" NAME="C_CLKOUT8_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="46" NAME="C_CLKOUT8_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="47" NAME="C_CLKOUT8_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="48" NAME="C_CLKOUT8_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="49" NAME="C_CLKOUT8_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="50" NAME="C_CLKOUT9_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="51" NAME="C_CLKOUT9_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="52" NAME="C_CLKOUT9_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="53" NAME="C_CLKOUT9_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="54" NAME="C_CLKOUT9_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION> Varaible Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="55" NAME="C_CLKOUT10_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="56" NAME="C_CLKOUT10_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="57" NAME="C_CLKOUT10_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="58" NAME="C_CLKOUT10_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="59" NAME="C_CLKOUT10_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="60" NAME="C_CLKOUT11_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="61" NAME="C_CLKOUT11_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="62" NAME="C_CLKOUT11_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="63" NAME="C_CLKOUT11_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="64" NAME="C_CLKOUT11_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="65" NAME="C_CLKOUT12_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="66" NAME="C_CLKOUT12_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="67" NAME="C_CLKOUT12_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="68" NAME="C_CLKOUT12_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="69" NAME="C_CLKOUT12_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION> Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="70" NAME="C_CLKOUT13_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="71" NAME="C_CLKOUT13_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="72" NAME="C_CLKOUT13_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="73" NAME="C_CLKOUT13_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="74" NAME="C_CLKOUT13_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="75" NAME="C_CLKOUT14_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="76" NAME="C_CLKOUT14_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="77" NAME="C_CLKOUT14_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="78" NAME="C_CLKOUT14_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="79" NAME="C_CLKOUT14_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="80" NAME="C_CLKOUT15_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="81" NAME="C_CLKOUT15_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="82" NAME="C_CLKOUT15_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="83" NAME="C_CLKOUT15_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="84" NAME="C_CLKOUT15_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION> Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="85" NAME="C_CLKFBIN_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="86" NAME="C_CLKFBIN_DESKEW" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Clock Deskew</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="87" NAME="C_CLKFBOUT_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="88" NAME="C_CLKFBOUT_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="89" NAME="C_CLKFBOUT_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="90" NAME="C_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="91" NAME="C_PSDONE_GROUP" TYPE="STRING" VALUE="MMCM0"><DESCRIPTION>Variable Phase Shift</DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="24" MPD_INDEX="92" NAME="C_EXT_RESET_HIGH" VALUE="1"><DESCRIPTION>External Reset</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="93" NAME="C_CLK_GEN" VALUE="UPDATE"><DESCRIPTION>C_CLK_GEN</DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT CLKFREQUENCY="200000000" DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="0" MSB="0" NAME="CLKIN" RIGHT="0" SIGIS="CLK" SIGNAME="dcm_clk_s"/><PORT CLKFREQUENCY="100000000" DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="1" MPD_INDEX="1" MSB="0" NAME="CLKOUT0" RIGHT="0" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0"/><PORT CLKFREQUENCY="200000000" DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="2" MPD_INDEX="2" MSB="0" NAME="CLKOUT1" RIGHT="0" SIGIS="CLK" SIGNAME="clk_200_0000MHzMMCM0"/><PORT CLKFREQUENCY="400000000" DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="3" MPD_INDEX="3" MSB="0" NAME="CLKOUT2" RIGHT="0" SIGIS="CLK" SIGNAME="clk_400_0000MHzMMCM0"/><PORT CLKFREQUENCY="400000000" DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="4" MPD_INDEX="4" MSB="0" NAME="CLKOUT3" RIGHT="0" SIGIS="CLK" SIGNAME="clk_400_0000MHzMMCM0_nobuf_varphase"/><PORT CLKFREQUENCY="150000000" DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="5" MPD_INDEX="5" MSB="0" NAME="CLKOUT4" RIGHT="0" SIGIS="CLK" SIGNAME="clk_150_0000MHz"/><PORT CLKFREQUENCY="200000000" DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="6" MPD_INDEX="19" MSB="0" NAME="PSCLK" RIGHT="0" SIGIS="CLK" SIGNAME="clk_200_0000MHzMMCM0"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="7" MPD_INDEX="20" MSB="0" NAME="PSEN" RIGHT="0" SIGNAME="MPMC_DCM_PSEN"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="8" MPD_INDEX="21" MSB="0" NAME="PSINCDEC" RIGHT="0" SIGNAME="MPMC_DCM_PSINCDEC"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="9" MPD_INDEX="22" MSB="0" NAME="PSDONE" RIGHT="0" SIGNAME="MPMC_DCM_PSDONE"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="10" MPD_INDEX="23" MSB="0" NAME="RST" RIGHT="0" SIGIS="RST" SIGNAME="sys_rst_s"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="11" MPD_INDEX="24" MSB="0" NAME="LOCKED" RIGHT="0" SIGNAME="Dcm_all_locked"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="6" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="__NOC__"/></PORTS><BUSINTERFACES/></MODULE><MODULE HWVERSION="1.00.g" INSTANCE="mdm_0" IPTYPE="PERIPHERAL" MHS_INDEX="12" MODCLASS="DEBUG" MODTYPE="mdm"><DESCRIPTION TYPE="SHORT">MicroBlaze Debug Module (MDM)</DESCRIPTION><DESCRIPTION TYPE="LONG">Debug module for MicroBlaze Soft Processor.</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="/raid/opt.x86_64/xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_g/doc/mdm.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6"><DESCRIPTION>Device Family</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="1" NAME="C_JTAG_CHAIN" TYPE="INTEGER" VALUE="2"><DESCRIPTION>Specifies the JTAG user-defined register used </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="2" NAME="C_INTERCONNECT" TYPE="INTEGER" VALUE="1"><DESCRIPTION>Specifies the Bus Interface for the JTAG UART </DESCRIPTION></PARAMETER><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="3" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x84400000"><DESCRIPTION>Base Address</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="4" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x8440ffff"><DESCRIPTION>High Address</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="5" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>PLB Address Bus Width</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="64"><DESCRIPTION>PLB Data Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"><DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"><DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="2"><DESCRIPTION>Number of PLB Masters</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="10" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="11" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"><DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="12" NAME="C_OPB_DWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>OPB Data Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="13" NAME="C_OPB_AWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>OPB Address Bus Width</DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="14" NAME="C_MB_DBG_PORTS" TYPE="INTEGER" VALUE="1"><DESCRIPTION>Number of MicroBlaze debug ports </DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="15" NAME="C_USE_UART" TYPE="INTEGER" VALUE="1"><DESCRIPTION>Enable JTAG UART </DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="16" NAME="C_UART_WIDTH" TYPE="INTEGER" VALUE="8"><DESCRIPTION>UART Data size </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="17" NAME="C_WRITE_FSL_PORTS" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Enable Write FSL Port</DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="1" MSB="0" NAME="Debug_SYS_Rst" RIGHT="0" SIGNAME="Debug_SYS_Rst"/><PORT DIR="O" MPD_INDEX="0" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/><PORT DEF_SIGNAME="Ext_BRK" DIR="O" MPD_INDEX="2" NAME="Ext_BRK" SIGNAME="Ext_BRK"/><PORT DEF_SIGNAME="Ext_NM_BRK" DIR="O" MPD_INDEX="3" NAME="Ext_NM_BRK" SIGNAME="Ext_NM_BRK"/><PORT BUS="SPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="4" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="5" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="8" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="9" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="10" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="11" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="12" MSB="0" NAME="PLB_masterID" RIGHT="0" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="13" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="14" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="15" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="16" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="17" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="18" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="19" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="20" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="21" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="22" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="23" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="24" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="25" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="26" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="28" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="29" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="30" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="31" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="32" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="33" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="34" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="35" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="36" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="37" MSB="0" NAME="Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="38" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="39" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="40" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="41" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="42" MSB="0" NAME="Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="43" MSB="0" NAME="Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="44" MSB="0" NAME="Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="OPB_Clk" SIGIS="CLK" SIGNAME="__NOC__"/><PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="47" NAME="OPB_Rst" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="48" MSB="0" NAME="OPB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_OPB_AWIDTH-1]"/><PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="49" MSB="0" NAME="OPB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:C_OPB_DWIDTH/8-1]"/><PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="OPB_RNW" SIGNAME="__NOC__"/><PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="OPB_select" SIGNAME="__NOC__"/><PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="OPB_seqAddr" SIGNAME="__NOC__"/><PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="53" MSB="0" NAME="OPB_DBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_OPB_DWIDTH-1]"/><PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="54" MSB="0" NAME="MDM_DBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_OPB_DWIDTH-1]"/><PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="55" NAME="MDM_errAck" SIGNAME="__NOC__"/><PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="56" NAME="MDM_retry" SIGNAME="__NOC__"/><PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="MDM_toutSup" SIGNAME="__NOC__"/><PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="58" NAME="MDM_xferAck" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Clk" DIR="O" MPD_INDEX="59" NAME="Dbg_Clk_0" SIGNAME="microblaze_0_mdm_bus_Dbg_Clk"/><PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_TDI" DIR="O" MPD_INDEX="60" NAME="Dbg_TDI_0" SIGNAME="microblaze_0_mdm_bus_Dbg_TDI"/><PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_TDO" DIR="I" MPD_INDEX="61" NAME="Dbg_TDO_0" SIGNAME="microblaze_0_mdm_bus_Dbg_TDO"/><PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Reg_En" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="62" MSB="0" NAME="Dbg_Reg_En_0" RIGHT="4" SIGNAME="microblaze_0_mdm_bus_Dbg_Reg_En" VECFORMULA="[0:4]"/><PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Capture" DIR="O" MPD_INDEX="63" NAME="Dbg_Capture_0" SIGNAME="microblaze_0_mdm_bus_Dbg_Capture"/><PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Shift" DIR="O" MPD_INDEX="64" NAME="Dbg_Shift_0" SIGNAME="microblaze_0_mdm_bus_Dbg_Shift"/><PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Update" DIR="O" MPD_INDEX="65" NAME="Dbg_Update_0" SIGNAME="microblaze_0_mdm_bus_Dbg_Update"/><PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Debug_Rst" DIR="O" MPD_INDEX="66" NAME="Dbg_Rst_0" SIGNAME="microblaze_0_mdm_bus_Debug_Rst"/><PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="67" NAME="Dbg_Clk_1" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="68" NAME="Dbg_TDI_1" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="69" NAME="Dbg_TDO_1" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="70" MSB="0" NAME="Dbg_Reg_En_1" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/><PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="Dbg_Capture_1" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="72" NAME="Dbg_Shift_1" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="73" NAME="Dbg_Update_1" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="74" NAME="Dbg_Rst_1" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="Dbg_Clk_2" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="76" NAME="Dbg_TDI_2" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="77" NAME="Dbg_TDO_2" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="78" MSB="0" NAME="Dbg_Reg_En_2" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/><PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="79" NAME="Dbg_Capture_2" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="80" NAME="Dbg_Shift_2" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="81" NAME="Dbg_Update_2" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="82" NAME="Dbg_Rst_2" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="83" NAME="Dbg_Clk_3" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="84" NAME="Dbg_TDI_3" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="85" NAME="Dbg_TDO_3" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="86" MSB="0" NAME="Dbg_Reg_En_3" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/><PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="87" NAME="Dbg_Capture_3" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="Dbg_Shift_3" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="89" NAME="Dbg_Update_3" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="90" NAME="Dbg_Rst_3" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="91" NAME="Dbg_Clk_4" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="92" NAME="Dbg_TDI_4" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="93" NAME="Dbg_TDO_4" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="94" MSB="0" NAME="Dbg_Reg_En_4" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/><PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="95" NAME="Dbg_Capture_4" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="Dbg_Shift_4" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="Dbg_Update_4" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="98" NAME="Dbg_Rst_4" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="Dbg_Clk_5" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="100" NAME="Dbg_TDI_5" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="101" NAME="Dbg_TDO_5" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="102" MSB="0" NAME="Dbg_Reg_En_5" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/><PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="103" NAME="Dbg_Capture_5" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="104" NAME="Dbg_Shift_5" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="Dbg_Update_5" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="Dbg_Rst_5" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="107" NAME="Dbg_Clk_6" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="Dbg_TDI_6" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="Dbg_TDO_6" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="110" MSB="0" NAME="Dbg_Reg_En_6" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/><PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="111" NAME="Dbg_Capture_6" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="112" NAME="Dbg_Shift_6" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="Dbg_Update_6" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="114" NAME="Dbg_Rst_6" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="115" NAME="Dbg_Clk_7" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="116" NAME="Dbg_TDI_7" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="117" NAME="Dbg_TDO_7" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="118" MSB="0" NAME="Dbg_Reg_En_7" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/><PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="119" NAME="Dbg_Capture_7" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="120" NAME="Dbg_Shift_7" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="121" NAME="Dbg_Update_7" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="122" NAME="Dbg_Rst_7" SIGNAME="__NOC__"/><PORT DEF_SIGNAME="bscan_tdi" DIR="O" MPD_INDEX="123" NAME="bscan_tdi" SIGNAME="bscan_tdi"/><PORT DEF_SIGNAME="bscan_reset" DIR="O" MPD_INDEX="124" NAME="bscan_reset" SIGNAME="bscan_reset"/><PORT DEF_SIGNAME="bscan_shift" DIR="O" MPD_INDEX="125" NAME="bscan_shift" SIGNAME="bscan_shift"/><PORT DEF_SIGNAME="bscan_update" DIR="O" MPD_INDEX="126" NAME="bscan_update" SIGNAME="bscan_update"/><PORT DEF_SIGNAME="bscan_capture" DIR="O" MPD_INDEX="127" NAME="bscan_capture" SIGNAME="bscan_capture"/><PORT DEF_SIGNAME="bscan_sel1" DIR="O" MPD_INDEX="128" NAME="bscan_sel1" SIGNAME="bscan_sel1"/><PORT DEF_SIGNAME="bscan_drck1" DIR="O" MPD_INDEX="129" NAME="bscan_drck1" SIGNAME="bscan_drck1"/><PORT DEF_SIGNAME="bscan_tdo1" DIR="I" MPD_INDEX="130" NAME="bscan_tdo1" SIGNAME="bscan_tdo1"/><PORT BUS="SFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="131" NAME="FSL0_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/><PORT BUS="SFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="132" NAME="FSL0_S_READ" SIGNAME="__NOC__"/><PORT BUS="SFSL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="133" MSB="0" NAME="FSL0_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/><PORT BUS="SFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="134" NAME="FSL0_S_CONTROL" SIGNAME="__NOC__"/><PORT BUS="SFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="135" NAME="FSL0_S_EXISTS" SIGNAME="__NOC__"/><PORT BUS="MFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="136" NAME="FSL0_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/><PORT BUS="MFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="137" NAME="FSL0_M_WRITE" SIGNAME="__NOC__"/><PORT BUS="MFSL0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="138" MSB="0" NAME="FSL0_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/><PORT BUS="MFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="139" NAME="FSL0_M_CONTROL" SIGNAME="__NOC__"/><PORT BUS="MFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="140" NAME="FSL0_M_FULL" SIGNAME="__NOC__"/><PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="141" NAME="Ext_JTAG_DRCK" SIGNAME="__NOC__"/><PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="142" NAME="Ext_JTAG_RESET" SIGNAME="__NOC__"/><PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="143" NAME="Ext_JTAG_SEL" SIGNAME="__NOC__"/><PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="144" NAME="Ext_JTAG_CAPTURE" SIGNAME="__NOC__"/><PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="145" NAME="Ext_JTAG_SHIFT" SIGNAME="__NOC__"/><PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="146" NAME="Ext_JTAG_UPDATE" SIGNAME="__NOC__"/><PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="147" NAME="Ext_JTAG_TDI" SIGNAME="__NOC__"/><PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="148" NAME="Ext_JTAG_TDO" SIGNAME="__NOC__"/></PORTS><BUSINTERFACES><BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="microblaze_0_mdm_bus" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG2" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="4" NAME="MBDEBUG_0" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="OPB" BUSSTD_PSF="OPB" IS_VALID="FALSE" MPD_INDEX="1" NAME="SOPB" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="2" NAME="SFSL0" TYPE="SLAVE"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="3" NAME="MFSL0" TYPE="MASTER"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG2" IS_VALID="FALSE" MPD_INDEX="5" NAME="MBDEBUG_1" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG2" IS_VALID="FALSE" MPD_INDEX="6" NAME="MBDEBUG_2" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG2" IS_VALID="FALSE" MPD_INDEX="7" NAME="MBDEBUG_3" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG2" IS_VALID="FALSE" MPD_INDEX="8" NAME="MBDEBUG_4" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG2" IS_VALID="FALSE" MPD_INDEX="9" NAME="MBDEBUG_5" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG2" IS_VALID="FALSE" MPD_INDEX="10" NAME="MBDEBUG_6" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG2" IS_VALID="FALSE" MPD_INDEX="11" NAME="MBDEBUG_7" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_BSCAN" MPD_INDEX="12" NAME="XMTC" TYPE="INITIATOR"/></BUSINTERFACES><MEMORYMAP><MEMRANGE BASEDECIMAL="2218786816" BASENAME="C_BASEADDR" BASEVALUE="0x84400000" HIGHDECIMAL="2218852351" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8440ffff" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K"><SLAVES><SLAVE BUSINTERFACE="SPLB"/><SLAVE BUSINTERFACE="SOPB"/></SLAVES></MEMRANGE></MEMORYMAP></MODULE><MODULE HWVERSION="2.00.a" INSTANCE="proc_sys_reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="13" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset"><DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION><DESCRIPTION TYPE="LONG">Reset management module</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="/raid/opt.x86_64/xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v2_00_a/doc/proc_sys_reset.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="lx"><DESCRIPTION>Device Subfamily</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4"><DESCRIPTION>Number of Clocks Before Input Change is Recognized On The External Reset Input </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="2" NAME="C_AUX_RST_WIDTH" TYPE="integer" VALUE="4"><DESCRIPTION>Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input </DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="std_logic" VALUE="1"><DESCRIPTION>External Reset Active High </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="4" NAME="C_AUX_RESET_HIGH" TYPE="std_logic" VALUE="1"><DESCRIPTION>Auxiliary Reset Active High </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="5" NAME="C_NUM_BUS_RST" TYPE="integer" VALUE="1"><DESCRIPTION>Number of Bus Structure Reset Registered Outputs </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="6" NAME="C_NUM_PERP_RST" TYPE="integer" VALUE="1"><DESCRIPTION>Number of Peripheral Reset Registered Outputs </DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" VALUE="virtex6"><DESCRIPTION>Device Family</DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT CLKFREQUENCY="100000000" DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="0" MSB="0" NAME="Slowest_sync_clk" RIGHT="0" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="1" MPD_INDEX="1" MSB="0" NAME="Ext_Reset_In" RIGHT="0" SIGIS="RST" SIGNAME="sys_rst_s"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="2" MPD_INDEX="3" MSB="0" NAME="MB_Debug_Sys_Rst" RIGHT="0" SIGIS="RST" SIGNAME="Debug_SYS_Rst"/><PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="3" MPD_INDEX="10" MSB="0" NAME="Dcm_locked" RIGHT="0" SIGNAME="Dcm_all_locked"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="4" MPD_INDEX="17" MSB="0" NAME="MB_Reset" RIGHT="0" SIGIS="RST" SIGNAME="mb_reset"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="5" MPD_INDEX="18" MSB="0" NAME="Bus_Struct_Reset" RIGHT="0" SIGIS="RST" SIGNAME="sys_bus_reset" VECFORMULA="[0:C_NUM_BUS_RST-1]"/><PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="6" MPD_INDEX="19" MSB="0" NAME="Peripheral_Reset" RIGHT="0" SIGIS="RST" SIGNAME="sys_periph_reset" VECFORMULA="[0:C_NUM_PERP_RST-1]"/><PORT DIR="I" MPD_INDEX="2" NAME="Aux_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="Core_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="Chip_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="6" NAME="System_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="Core_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="Chip_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="System_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="11" NAME="RstcPPCresetcore_0" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="12" NAME="RstcPPCresetchip_0" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="13" NAME="RstcPPCresetsys_0" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="RstcPPCresetcore_1" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="RstcPPCresetchip_1" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="RstcPPCresetsys_1" SIGIS="RST" SIGNAME="__NOC__"/></PORTS><BUSINTERFACES><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="0" NAME="RESETPPC0" TYPE="INITIATOR"/><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="1" NAME="RESETPPC1" TYPE="INITIATOR"/></BUSINTERFACES></MODULE><MODULE HWVERSION="1.04.a" INSTANCE="chipscope_icon_0" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="IP" MODTYPE="chipscope_icon"><DESCRIPTION TYPE="SHORT">Chipscope Integrated Controller</DESCRIPTION><DESCRIPTION TYPE="LONG">'The Chipscope ICON core provides a communication path between the FPGA Boundary Scan port and the other Chipscope Cores OPB IBA, PLB IBA, VIO, and the ILA.'</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="/raid/opt.x86_64/xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/chipscope_icon_v1_04_a/doc/chipscope_icon.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="string" VALUE="virtex6"><DESCRIPTION>Device Family</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="string" VALUE="6vlx240t"><DESCRIPTION>Device Name</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PACKAGE" TYPE="string" VALUE="ff1156"><DESCRIPTION>Package Name</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPEEDGRADE" TYPE="string" VALUE="-1"><DESCRIPTION>Speed Grade Name</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="C_NUM_CONTROL_PORTS" TYPE="integer" VALUE="9"><DESCRIPTION>Number of Control Ports </DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_SYSTEM_CONTAINS_MDM" TYPE="integer" VALUE="1"><DESCRIPTION>System Contains MDM Peripheral or Not </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="6" NAME="C_FORCE_BSCAN_USER_PORT" TYPE="integer" VALUE="1"><DESCRIPTION>Use a specific BSCAN user port</DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="35" LSB="0" MHS_INDEX="0" MPD_INDEX="0" MSB="35" NAME="control0" RIGHT="0" SIGNAME="oob_control_ila_control" VECFORMULA="[35:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="35" LSB="0" MHS_INDEX="1" MPD_INDEX="1" MSB="35" NAME="control1" RIGHT="0" SIGNAME="sata_phy_ila_control" VECFORMULA="[35:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="35" LSB="0" MHS_INDEX="2" MPD_INDEX="2" MSB="35" NAME="control2" RIGHT="0" SIGNAME="sata_rx_frame_ila_control" VECFORMULA="[35:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="35" LSB="0" MHS_INDEX="3" MPD_INDEX="3" MSB="35" NAME="control3" RIGHT="0" SIGNAME="sata_tx_frame_ila_control" VECFORMULA="[35:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="35" LSB="0" MHS_INDEX="4" MPD_INDEX="4" MSB="35" NAME="control4" RIGHT="0" SIGNAME="cmd_layer_ila_control" VECFORMULA="[35:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="35" LSB="0" MHS_INDEX="5" MPD_INDEX="5" MSB="35" NAME="control5" RIGHT="0" SIGNAME="user_logic_ila_control" VECFORMULA="[35:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="35" LSB="0" MHS_INDEX="6" MPD_INDEX="6" MSB="35" NAME="control6" RIGHT="0" SIGNAME="npi_ila_control" VECFORMULA="[35:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="35" LSB="0" MHS_INDEX="7" MPD_INDEX="7" MSB="35" NAME="control7" RIGHT="0" SIGNAME="npi_if_ila_control" VECFORMULA="[35:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="35" LSB="0" MHS_INDEX="8" MPD_INDEX="8" MSB="35" NAME="control8" RIGHT="0" SIGNAME="npi_if_tx_ila_control" VECFORMULA="[35:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="35" LSB="0" MPD_INDEX="9" MSB="35" NAME="control9" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[35:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="35" LSB="0" MPD_INDEX="10" MSB="35" NAME="control10" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[35:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="35" LSB="0" MPD_INDEX="11" MSB="35" NAME="control11" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[35:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="35" LSB="0" MPD_INDEX="12" MSB="35" NAME="control12" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[35:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="35" LSB="0" MPD_INDEX="13" MSB="35" NAME="control13" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[35:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="35" LSB="0" MPD_INDEX="14" MSB="35" NAME="control14" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[35:0]"/><PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="35" LSB="0" MPD_INDEX="15" MSB="35" NAME="control15" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[35:0]"/><PORT DEF_SIGNAME="bscan_tdi" DIR="I" MPD_INDEX="16" NAME="tdi_in" SIGNAME="bscan_tdi"/><PORT DEF_SIGNAME="bscan_reset" DIR="I" MPD_INDEX="17" NAME="reset_in" SIGNAME="bscan_reset"/><PORT DEF_SIGNAME="bscan_shift" DIR="I" MPD_INDEX="18" NAME="shift_in" SIGNAME="bscan_shift"/><PORT DEF_SIGNAME="bscan_update" DIR="I" MPD_INDEX="19" NAME="update_in" SIGNAME="bscan_update"/><PORT DEF_SIGNAME="bscan_sel1" DIR="I" MPD_INDEX="20" NAME="sel_in" SIGNAME="bscan_sel1"/><PORT DEF_SIGNAME="bscan_drck1" DIR="I" MPD_INDEX="21" NAME="drck_in" SIGNAME="bscan_drck1"/><PORT DEF_SIGNAME="bscan_tdo1" DIR="O" MPD_INDEX="22" NAME="tdo_out" SIGNAME="bscan_tdo1"/></PORTS><BUSINTERFACES/></MODULE></MODULES></EDKSYSTEM>