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https://opencores.org/ocsvn/sata_controller_core/sata_controller_core/trunk
Subversion Repositories sata_controller_core
[/] [sata_controller_core/] [trunk/] [sata2_fifo_v1_00_a/] [doc/] [README] - Rev 7
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The SATA2 core implements the Command, Transport and Link Layers of
the SATA2 protocol and provides a Physical Layer Wrapper for
the transceivers.
The Design source files can be found under 'hdl/vhdl' and
'hdl/verilog' directories
/hdl/vhdl:
sata_core.vhd
_________|__________
| |
command_layer.vhd sata_link_layer.vhd
_________________________|________
| | | |
sata_phy.v scrambler.vhd crc.vhd mux_161.vhd
hdl/verilog:
sata_phy.v
_________|________________________________
| | |
oob_control.v sata_gtx_dual.v mgt_usrclk_source_mmcm.v
____|_____ |
| | sata_gtx.v
mux_41.v mux_21.v
The synthesis Makefile is under 'syn' and the coregen netlist
Makefile for FIFOs is under 'netlist'
Notes:
* To use with Xilinx Virtex6 ML605 board -
Supply a 150 MHz reference clock for the GTX transceivers. This can be
done by dividing the 200 MHz reference clock on the ML605 board or by
configuring the programmable clock sources on the FMC XM104 connectivity
card.
* After providing a reset, check for the LINKUP signal before using the
core. The OOB controller asserts LINKUP after completing the link
initialization and synchronization process.
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