Subversion Repositories sata_controller_core

# SATA Port J11                     #J64 FMC pins
Net TXN0_OUT             LOC = AF2;   #A27 
Net TXP0_OUT             LOC = AF1;   #A26
Net RXN0_IN              LOC = AF6;   #A7
Net RXP0_IN              LOC = AF5;   #A6

#Net FMC_HPC_DP2_C2M_N    LOC = AF2;   #A27
#Net FMC_HPC_DP2_C2M_P    LOC = AF1;   #A26
#Net FMC_HPC_DP2_M2C_N    LOC = AF6;   #A7
#Net FMC_HPC_DP2_M2C_P    LOC = AF5;   #A6


# GTX Clock Module constraints 
#NET REFCLK_PAD_N_IN  LOC=AK5; #FMC_HPC_CLK2_M2C_MGT_C_N
#NET REFCLK_PAD_P_IN  LOC=AK6; #FMC_HPC_CLK2_M2C_MGT_C_P

#### Module LEDs_8Bit constraints
NET     PLLLKDET_OUT_N          LOC= "AC22" |IOSTANDARD=LVCMOS25;       #LED 0
NET     DCMLOCKED_OUT           LOC= "AC24" |IOSTANDARD=LVCMOS25;       #LED 1
NET     LINKUP                  LOC= "AE22" |IOSTANDARD=LVCMOS25;       #LED 2

################################## Clock Constraints ##########################

  # Change this to the 150 Mhz GTX reference clock  
Net CLKIN_150 TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz;
Net CLKIN_150 LOC = J9  ;
#Net CLKIN_150 LOC = J9  |  IOSTANDARD=LVDS_25  |  DIFF_TERM = TRUE;
#Net CLKIN_N LOC = H9  |  IOSTANDARD=LVDS_25  |  DIFF_TERM = TRUE;

Net reset TIG;
Net reset LOC = H10  |  IOSTANDARD=SSTL15  |  PULLUP  |  TIG;