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[/] [saturn/] [trunk/] [FPGA MIOSIL4/] [fpga_miosil4/] [fpga_miosil4.gise] - Rev 7

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">

  <!--                                                          -->

  <!--             For tool use only. Do not edit.              -->

  <!--                                                          -->

  <!-- ProjectNavigator created generated project file.         -->

  <!-- For use in tracking generated file and other information -->

  <!-- allowing preservation of process status.                 -->

  <!--                                                          -->

  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->

  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>

  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fpga_miosil4.xise"/>

  <files xmlns="http://www.xilinx.com/XMLSchema">
    <file xil_pn:fileType="FILE_ASY" xil_pn:name="../../IPCommunication/dpram.asy" xil_pn:origination="imported"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../../IPCommunication/dpram.ngc" xil_pn:origination="imported"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../../IPCommunication/dpram.vhd" xil_pn:origination="imported"/>
    <file xil_pn:fileType="FILE_VHO" xil_pn:name="../../IPCommunication/dpram.vho" xil_pn:origination="imported"/>
    <file xil_pn:fileType="FILE_ASY" xil_pn:name="../../IPCommunication/fifo_copy.asy" xil_pn:origination="imported"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../../IPCommunication/fifo_copy.ngc" xil_pn:origination="imported"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../../IPCommunication/fifo_copy.vhd" xil_pn:origination="imported"/>
    <file xil_pn:fileType="FILE_VHO" xil_pn:name="../../IPCommunication/fifo_copy.vho" xil_pn:origination="imported"/>
    <file xil_pn:fileType="FILE_ASY" xil_pn:name="../../IPCommunication/fifo_spi.asy" xil_pn:origination="imported"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../../IPCommunication/fifo_spi.ngc" xil_pn:origination="imported"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../../IPCommunication/fifo_spi.vhd" xil_pn:origination="imported"/>
    <file xil_pn:fileType="FILE_VHO" xil_pn:name="../../IPCommunication/fifo_spi.vho" xil_pn:origination="imported"/>
    <file xil_pn:fileType="FILE_ASY" xil_pn:name="../../IPCommunication/fifo_tx.asy" xil_pn:origination="imported"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../../IPCommunication/fifo_tx.ngc" xil_pn:origination="imported"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../../IPCommunication/fifo_tx.vhd" xil_pn:origination="imported"/>
    <file xil_pn:fileType="FILE_VHO" xil_pn:name="../../IPCommunication/fifo_tx.vho" xil_pn:origination="imported"/>
    <file xil_pn:fileType="FILE_ASY" xil_pn:name="../../IPCommunication/fiforx_spi.asy" xil_pn:origination="imported"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../../IPCommunication/fiforx_spi.ngc" xil_pn:origination="imported"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../../IPCommunication/fiforx_spi.vhd" xil_pn:origination="imported"/>
    <file xil_pn:fileType="FILE_VHO" xil_pn:name="../../IPCommunication/fiforx_spi.vho" xil_pn:origination="imported"/>
    <file xil_pn:fileType="FILE_ASY" xil_pn:name="../../IPCommunication/fifotx_spi.asy" xil_pn:origination="imported"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../../IPCommunication/fifotx_spi.ngc" xil_pn:origination="imported"/>
    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="../../IPCommunication/fifotx_spi.sym" xil_pn:origination="imported"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../../IPCommunication/fifotx_spi.vhd" xil_pn:origination="imported"/>
    <file xil_pn:fileType="FILE_VHO" xil_pn:name="../../IPCommunication/fifotx_spi.vho" xil_pn:origination="imported"/>
    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="top_miosil4.bgn" xil_pn:subbranch="FPGAConfiguration"/>
    <file xil_pn:fileType="FILE_BIN" xil_pn:name="top_miosil4.bin"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="top_miosil4.bit" xil_pn:subbranch="FPGAConfiguration"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="top_miosil4.bld"/>
    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="top_miosil4.cmd_log"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="top_miosil4.drc" xil_pn:subbranch="FPGAConfiguration"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="top_miosil4.lso"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_IMPACT_MISC" xil_pn:name="top_miosil4.mcs"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="top_miosil4.ncd" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="top_miosil4.ngc"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="top_miosil4.ngd"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="top_miosil4.ngr"/>
    <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="top_miosil4.pad"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="top_miosil4.par" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="top_miosil4.pcf" xil_pn:subbranch="Map"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="top_miosil4.prj"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_IMPACT_MISC" xil_pn:name="top_miosil4.prm"/>
    <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="top_miosil4.ptwx"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="top_miosil4.stx"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="top_miosil4.syr"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TSI_REPORT" xil_pn:name="top_miosil4.tsi" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="top_miosil4.twr" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="top_miosil4.twx" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="top_miosil4.unroutes" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="top_miosil4.ut" xil_pn:subbranch="FPGAConfiguration"/>
    <file xil_pn:fileType="FILE_XPI" xil_pn:name="top_miosil4.xpi"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="top_miosil4.xst"/>
    <file xil_pn:fileType="FILE_HTML" xil_pn:name="top_miosil4_envsettings.html"/>
    <file xil_pn:fileType="FILE_NCD" xil_pn:name="top_miosil4_guide.ncd" xil_pn:origination="imported"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="top_miosil4_map.map" xil_pn:subbranch="Map"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="top_miosil4_map.mrp" xil_pn:subbranch="Map"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="top_miosil4_map.ncd" xil_pn:subbranch="Map"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="top_miosil4_map.ngm" xil_pn:subbranch="Map"/>
    <file xil_pn:fileType="FILE_PSR" xil_pn:name="top_miosil4_map.psr"/>
    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_miosil4_map.xrpt"/>
    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_miosil4_ngdbuild.xrpt"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="top_miosil4_pad.csv" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="top_miosil4_pad.txt" xil_pn:subbranch="Par"/>
    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_miosil4_par.xrpt"/>
    <file xil_pn:fileType="FILE_HTML" xil_pn:name="top_miosil4_summary.html"/>
    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="top_miosil4_summary.xml"/>
    <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="top_miosil4_usage.xml"/>
    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_miosil4_xst.xrpt"/>
    <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
    <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
  </files>

  <transforms xmlns="http://www.xilinx.com/XMLSchema">
    <transform xil_pn:end_ts="1446560413" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1446560413">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1446560413" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1447385170099995465" xil_pn:start_ts="1446560413">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1446560425" xil_pn:in_ck="1952690310691631180" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2589080491559761581" xil_pn:start_ts="1446560413">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="../../IPCommunication/dpram.ngc"/>
      <outfile xil_pn:name="../../IPCommunication/dpram.vhd"/>
      <outfile xil_pn:name="../../IPCommunication/fifo_copy.ngc"/>
      <outfile xil_pn:name="../../IPCommunication/fifo_copy.vhd"/>
      <outfile xil_pn:name="../../IPCommunication/fifo_spi.ngc"/>
      <outfile xil_pn:name="../../IPCommunication/fifo_spi.vhd"/>
      <outfile xil_pn:name="../../IPCommunication/fifo_tx.ngc"/>
      <outfile xil_pn:name="../../IPCommunication/fifo_tx.vhd"/>
      <outfile xil_pn:name="../../IPCommunication/fiforx_spi.ngc"/>
      <outfile xil_pn:name="../../IPCommunication/fiforx_spi.vhd"/>
      <outfile xil_pn:name="../../IPCommunication/fifotx_spi.ngc"/>
      <outfile xil_pn:name="../../IPCommunication/fifotx_spi.vhd"/>
    </transform>
    <transform xil_pn:end_ts="1446560425" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1446560425">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1446560425" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="967335915756146635" xil_pn:start_ts="1446560425">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1446560425" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-5609353907947751920" xil_pn:start_ts="1446560425">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1446560425" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="7539475268990939549" xil_pn:start_ts="1446560425">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1449765150" xil_pn:in_ck="3145085651432349314" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2596630056137988500" xil_pn:start_ts="1449765123">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="OutputChanged"/>
      <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
      <outfile xil_pn:name="top_miosil4.lso"/>
      <outfile xil_pn:name="top_miosil4.ngc"/>
      <outfile xil_pn:name="top_miosil4.ngr"/>
      <outfile xil_pn:name="top_miosil4.prj"/>
      <outfile xil_pn:name="top_miosil4.stx"/>
      <outfile xil_pn:name="top_miosil4.syr"/>
      <outfile xil_pn:name="top_miosil4.xst"/>
      <outfile xil_pn:name="top_miosil4_xst.xrpt"/>
      <outfile xil_pn:name="webtalk_pn.xml"/>
      <outfile xil_pn:name="xst"/>
    </transform>
    <transform xil_pn:end_ts="1449768476" xil_pn:in_ck="6680943409366637823" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-1864011955707674208" xil_pn:start_ts="1449768476">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1449768484" xil_pn:in_ck="4657145349607151608" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-4507791154668227266" xil_pn:start_ts="1449768476">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_ngo"/>
      <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
      <outfile xil_pn:name="top_miosil4.bld"/>
      <outfile xil_pn:name="top_miosil4.ngd"/>
      <outfile xil_pn:name="top_miosil4_ngdbuild.xrpt"/>
    </transform>
    <transform xil_pn:end_ts="1449768626" xil_pn:in_ck="-7773210014958108295" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="3943244437903735591" xil_pn:start_ts="1449768484">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
      <outfile xil_pn:name="top_miosil4.pcf"/>
      <outfile xil_pn:name="top_miosil4_map.map"/>
      <outfile xil_pn:name="top_miosil4_map.mrp"/>
      <outfile xil_pn:name="top_miosil4_map.ncd"/>
      <outfile xil_pn:name="top_miosil4_map.ngm"/>
      <outfile xil_pn:name="top_miosil4_map.psr"/>
      <outfile xil_pn:name="top_miosil4_map.xrpt"/>
      <outfile xil_pn:name="top_miosil4_summary.xml"/>
      <outfile xil_pn:name="top_miosil4_usage.xml"/>
    </transform>
    <transform xil_pn:end_ts="1449768654" xil_pn:in_ck="8781845287253437042" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-7098172938909838473" xil_pn:start_ts="1449768626">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
      <outfile xil_pn:name="top_miosil4.ncd"/>
      <outfile xil_pn:name="top_miosil4.pad"/>
      <outfile xil_pn:name="top_miosil4.par"/>
      <outfile xil_pn:name="top_miosil4.ptwx"/>
      <outfile xil_pn:name="top_miosil4.unroutes"/>
      <outfile xil_pn:name="top_miosil4.xpi"/>
      <outfile xil_pn:name="top_miosil4_pad.csv"/>
      <outfile xil_pn:name="top_miosil4_pad.txt"/>
      <outfile xil_pn:name="top_miosil4_par.xrpt"/>
    </transform>
    <transform xil_pn:end_ts="1446560741" xil_pn:in_ck="6680943409366630198" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-3126680107772998300" xil_pn:start_ts="1446560711">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
      <status xil_pn:value="OutOfDateForInputs"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="InputChanged"/>
      <status xil_pn:value="InputRemoved"/>
      <status xil_pn:value="OutputRemoved"/>
    </transform>
    <transform xil_pn:end_ts="1443423668" xil_pn:in_ck="6680943409366617344" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8150872254684753111" xil_pn:start_ts="1443423477">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <status xil_pn:value="OutOfDateForInputs"/>
      <status xil_pn:value="OutOfDateForPredecessor"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="InputAdded"/>
      <status xil_pn:value="InputChanged"/>
      <status xil_pn:value="InputRemoved"/>
      <status xil_pn:value="OutputChanged"/>
      <status xil_pn:value="OutputRemoved"/>
    </transform>
    <transform xil_pn:end_ts="1449768654" xil_pn:in_ck="7528106365894670709" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="2711695571398334413" xil_pn:start_ts="1449768645">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
      <outfile xil_pn:name="top_miosil4.tsi"/>
      <outfile xil_pn:name="top_miosil4.twr"/>
      <outfile xil_pn:name="top_miosil4.twx"/>
    </transform>
  </transforms>

</generated_project>

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