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[/] [scarts/] [trunk/] [processor/] [workspace/] [terasic_de2-115/] [VHDL/] [altera_pll.ppf] - Rev 25

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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone IV E" variation_name="altera_pll" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="areset" direction="input" scope="external"  />
<pin name="inclk0" direction="input" scope="external" source="clock"  />
<pin name="c0" direction="output" scope="external" source="clock"  />
<pin name="locked" direction="output" scope="external"  />

</global>
</pinplan>

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