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; intrinsics support generator support routines.
; 
; This entire file is deeply littered with mep-specific logic. You have
; been warned.
;
; Copyright (C) 2000, 2001, 2002, 2003, 2009 Red Hat, Inc.
; This file is part of CGEN.
; Specify which application.
; String containing copyright text.
; String containing text defining the package we're generating code for.
; Initialize the options.
; include aliases
; do analyze the semantics
;; Shortcuts for commonly-used functions.
" ";; HELPER FUNCTIONS
;; ----------------
;; True if FN returns the same value for FIRST and SECOND.
;; True if predicate FN holds for both FIRST and SECOND.
;; True if FN holds for every element of LIST.
;; True if FN holds for one element of LIST.
;; True if LIST1 and LIST2 are the same length and (FN X Y) holds for
;; each (X Y) in the zipped list.
;; Use (SETTER ELEM INDEX) to assign some number INDEX to each element
;; ELEM of LIST.  BASE is the index of the first element; other elements
;; are numbered incrementally.  Return the first unused index value.
;; Apply FN to every list of arguments in ARGS.
;; Sort list ELEMS with partial order FN, where (FN X Y) is true iff X "<=" Y.
;; Generate preprocessor macro names, suitable for use as bitmasks.
"_";; Return an inclusive OR of every bitmask member in NAMES.
"0""|";; Assign values to every bitmask in NAMES.
"#define "" ""\n""\n";; Convert ISA symbol ISA into a target-frobbed string
;; PRETTY-PRINTER SUPPORT
;; ----------------------
;; How many spaces to indent the next line.
;; End the current line and indent the new one.
"\n";; Helper functions, useful as arguments to WRITE-LIST.
", "",";; Execute BODY so that every call to LINE-BREAK will indent by
;; INDENT more spaces than it does now.
;; Write PREFIX, then execute BODY so that every call to LINE-BREAK
;; will indent to the end of the prefix.  Write SUFFIX afterwards.
;;
;; This function should only be called at the start of a new line.
;; Write out each element of LIST individually using WRITE.  Use (BREAK)
;; to separate the elements.
;; Like WRITE-LIST, but write DUMMY if the list is empty.
;; MACROS
;; ------
;; little macro for making assoc tables with nice names
;; Make a very simple structure interface.  NAME is the structure's name
;; and FIELDS is a list of its fields.
;;
;;    (make-struct foo (f1 f2 f3 ...))
;;
;; defines the following functions:
;;
;;    (foo:make f1 f2 f3 ...)
;;	  Create a new object with the given values for fields F1, F2, F3...
;;
;;    (foo:f1 object)
;;	  Return the value of OBJECT's F1 field, or #f if OBJECT itself is #f.
;;
;;    (foo:set-f1! object value)
;;	  Set OBJECT's F1 field to VALUE.
;;
;; ... and likewise for the other fields.  Each structure is represented
;; as a vector of its elements.
;; MEP-SPECIFIC DETAILS
;; --------------------
;; Predicates for recognizing coprocessor register set hardware names.
;; HW is the hardware name: a symbol, or #:unbound in some cases.
;;
;; At the moment, we do this by looking at the hardware's name as a
;; string; it would be more graceful to handle this with an attribute.
;;
;; Older MeP .cpu files call the coprocessor register sets h-cr,
;; h-cr64, and h-ccr.  Newer versions of a2cgen suffix the hardware
;; names for the coprocessor's registers with the name of the
;; coprocessor, and the me_module number.  So, for example, if
;; me_module 3 has an rhcop coprocessor, its register sets will be
;; called h-cr64-rhcop-3, h-cr-rhcop-3, and h-ccr-rhcop-3.
;; Return a predicate that recognizes hardware names that start with
;; PREFIX.  PREFIX is a string, like "h-cr"; the returned predicate
;; will return true if its argument is the symbol whose name is
;; PREFIX, (e.g. 'h-cr), or any symbol whose name begins with PREFIX
;; followed by a hyphen (e.g. 'h-cr-rhcop-1).
;; Precompute some stuff.
"-""h-cr64""h-cr""h-ccr";; Return the gcc rtl mode that should be used for operand OP.
;; Return #f to use the default, target-independent choice.
"SI""SF""DI""SI""SI";; Return the list of arguments for an intrinsic function.  ARGUMENTS is
;; a list of the operands found in the instruction's syntax string, in the
;; order they appear.  OUTPUT-OPERANDS is a list of all the instruction's
;; output operands (no particular order).  Both lists contain md-operands.
;;
;; Normally ARGUMENTS itself is the correct return value, but we
;; need a couple of MeP-specific hacks:
;;
;;   - Instructions that write to r0 do not make r0 a syntactic
;;   operand.  Instead, they embed "\\$0" in the syntax string.
;;   Cope with this by adding $0 to the beginning of the list
;;   if written.
;;
;;   - $spr and $tpr can appear in the syntax string but are
;;   not supposed to be treated as arguments to the intrinsic.
;; Convert the given cgen ISA name into its gcc equivalent.
;; cgen names such as 'ext_core<X>' and 'ext_cop<X>_YY' become 'ext<X>'.
"ext_cop""ext""ext_core""ext";; Apply FN once for each ISA.  The first argument to FN is a user-readable
;; string that describes the ISA.  The second argument is the ISA name
;; returned by frob-isa-name.
"ext";; Return the number of the first register belonging to the given
;; hardware element.
; core registers
; control registers
; 32-bit coprocessor registers
; 64-bit coprocessor registers (same)
; coprocessor control registers
;; Return the constraint string for register operand OP.
"z""h";; hi
"l";; lo
;; "tiny" registers, in the range 0..7
"t""r"; core registers
"c"; control registers
; 32-bit coprocessor registers
; 64-bit coprocessor registers
"em""x""y"; coprocessor control registers
"r";; The first hard register available to the intrinsics generator.
;; The instructions mapped to a particular intrinsic can be subdivided
;; into groups, each representing a particular form of code generation.
;; In the MeP case, we have one group for __vliw functions and one group
;; for normal functions.
;; True if INSN belongs to GROUP, where GROUP is a membmer of TARGET:GROUPS.
;; Convert an intrinsic's cgen name into the name of its builtin function.
"mep_";; Helper functions for getting the values of certain mep-specific gcc
;; attributes.  In each case INSN is a cgen instruction (not an md-insn).
"yes""no""ext_core""core""cop""0""core";; Return the define_insn attributes for INSN as a list of (NAME . VALUE)
;; pairs.
"operand2";; Define target-specific fields of cgen_insn.  In the MeP case, we want
;; to record how long the intruction is.
"\n""  /* The length of the instruction, in bytes.  */\n""  int length;\n";; Initialize the fields described above.
;; Use WELL-KNOWN-INTRINSIC to define the names of builtins that
;; gcc might treat specially.
"3""i""i3""cadd""csub""cand""cor""cnor""cxor""csll""csrl""csra""cmov""cpmov""cmovi""cmov1""cmov2""cmovc1""cmovc2""cmovh1""cmovh2""cneg""cmula0""xmula0""cextuh""cextub""cexth""cextb""fmovs""fadds""TARGET_FMAX""fsubs""TARGET_FMAX""fmuls""TARGET_FMAX""fdivs""TARGET_FMAX""fsqrts""TARGET_FMAX""fabss""TARGET_FMAX""fnegs""TARGET_FMAX""ftruncws""TARGET_FMAX""fcvtsw""TARGET_FMAX""fcmpus""TARGET_FMAX""fcmpues""TARGET_FMAX""fcmpuls""TARGET_FMAX""fcmpules""TARGET_FMAX""fcmpes""TARGET_FMAX""fcmplis""TARGET_FMAX""fcmpleis""TARGET_FMAX";; INTRINSIC OPERANDS
;; ------------------
;;
;; Each intrinsic operand is represented by a unique MD-OPERAND.
;; These objects refer back to normal cgen operands but add the extra
;; information needed for intrinsics support.  Each MD-OPERAND belongs
;; to exactly one MD-INSN.
;;
;;    OP is the cgen operand
;;
;;    IFIELD-VALUE is the constant value that the instruction assigns
;;    to the operand's field, or #f if the field isn't constant.
;;
;;    ARG-INDEX is the position of this operand in the intrinsic's
;;    argument list, or #f if the operand is not an argument.
;;
;;    READ-INDEX is the match_operand number assigned to this operand
;;    when it appears in a right-hand context.  The value is #f if we
;;    never generate such a match_operand, either because the operand
;;    is a strict lvalue or because ARG-INDEX is #f.
;;
;;    WRITE-INDEX is like READ-INDEX but is used for left-hand contexts.
;;
;;    MODE is the operand's gcc mode (SI, etc.).
;; Helper functions to extract commonly-used fields from the
;; underlying cgen operand.
;; Functions to access well-known operand attributes.
;; Return true if operand OP represents the program counter.
;; Return true if operand OP must be mapped to a label.  This is only
;; ever true of argument operands.
;; Return true if OP is an immediate operand.
;; Return true if operand OP is an index into a register file.  gcc will
;; convert them into REG rtxes.
;; If operand OP is a fixed hard register, return the number GCC assigns
;; to it, otherwise return #f.
;; SPECIFIC TO 32-BIT TARGETS
;; Guess the gcc rtl mode for operand OP.  First see whether it uses
;; a known hardware element, then try the CDATA attribute.
"HI""QI""SI";; Return true if operand OP is a signed immediate.
;; If OP accepts only CONST_INTs, return the lowest value it accepts.
;; Likewise the highest value + 1.
;; Return the name of an immediate predicate for operand OP, assuming
;; that OP should accept only CONST_INTs.  We define these predicates
;; in the gcc include file.
"cgen_""_""a""_immediate";; Return the match_operand predicate for operand OP.
"memory_operand""immediate_operand""nonimmediate_operand""general_operand";; Return the gcc rtx for non-argument operand OP.
"(mem:"" (scratch:SI))""(reg:"" "")""bad intrinsic operand \"""\": need constant or ifield indexed register, got ";; Return the constraint string for operand OP.  LVALUE? is true if the
;; operand is appearing in a left-hand context.  For read-write operands,
;; the rvalue operand should have a numerical constraint giving the
;; number of the lvalue.
"";; Return the rtl pattern for operand OP.  CONTEXT is LHS if the operand
;; is being used as an lvalue, RHS if it is being used as an rvalue in the
;; first set of a pattern and RHS-COPY if it is being used as an rvalue
;; in subsequent sets.
"(pc)""(match_dup "")""(match_operand:"" "" \"""\" \"""=""""\")";; GCC INSTRUCTION PATTERNS
;; ------------------------
;;
;; If we need to generate a define_insn pattern for a particular cgen
;; instruction, we will create a unique MD-INSN for it.  Each MD-INSN
;; is associated with a (shared) INTRINSIC object.
;;
;;    MD-NAME is the name of the define_insn pattern
;;
;;    INDEX is a unique number given to this instruction.  Instructions
;;    are numbered according to their position in the .md output file,
;;    the first instruction having index 0.
;;
;;    INTRINSIC is the intrinsic object to which this instruction belongs.
;;
;;    CGEN-INSN is the underlying cgen insn.
;;
;;    SYNTAX is the output of syntax-break-out with cgen operands
;;    converted to md-operands.
;;
;;    ARGUMENTS is a list of the operands that act as formal arguments
;;    to the intrinsic function.  Usually this is the same as SYNTAX
;;    with strings removed, but there can be target-specific reasons
;;    for using a different argument list.
;;
;;    INPUTS is a list of the operands that appear in a right-hand
;;    context within the define_insn pattern.  If a member of this
;;    list is also in ARGUMENTS, it will have a valid READ-INDEX.
;;
;;    OUTPUTS is like INPUTS except that it lists the operands that
;;    appear in a left-hand context.  Argument operands in this list
;;    will have a valid WRITE-INDEX.
;;
;;    OPERANDS is a concatenation of OUTPUTS and INPUTS.
;;
;;    CPTYPE is the type to use for coprocessor operands (like V4HI)
;;
;;    CRET? is set if the first argument is returned rather than passed.
;; Return the name of the underlying cgen insn, mostly used for
;; error reporting.
;; Return true if INSN is inherently volatile, meaning that it has
;; important effects that are not described by its gcc rtx pattern.
;; This is true for any instruction with the VOLATILE attribute,
;; any instruction without output operands (including those with
;; no semantics at all) and any instruction that reads from or
;; writes to a REGNUM operand.
;; Return the list of ISAs that implement INSN.  Ignore those that
;; were excluded on the command line.
;; The full list of instruction groups.  As well target-specific groups,
;; this includes "known-code", meaning that the instruction uses a specific
;; rtl code instead of an unspec.
;; Return the list of groups to which INSN belongs.
;; Partial ordering of syntax elements.  Return true if ELEM1 and ELEM2
;; are compatible and ELEM2's range is a superset of ELEM1's.  The rules
;; are that:
;;
;;    - Identical syntax strings are compatible.
;;
;;    - Immediate operands are compatible if the range of one is contained
;;    within the range of the other.
;;
;;    - Other types of operand are compatible if they use the same
;;    hardware element and have the same length.
;; Helper functions for comparing lists of operands or lists of syntax
;; pieces using the above ordering.
;; INTRINSICS
;; ----------
;;
;; Intrinsics have two names, the one that appears in the cgen file
;; and the one that is given to the builtin function.  The former is
;; its "cgen name" and is only relevant during the analysis phase.
;;
;;    NAME is the name of the intrinsic's builtin function.  It is
;;    generated from the cgen name by TARGET:BUILTIN-NAME.
;;
;;    INDEX is the index of this intrinsic in the global INTRINSICS list.
;;
;;    UNSPEC is the unspec number to use for the right hand side of the
;;    first SET pattern.  Add 2 for each subsequent output (so that real
;;    and shadow registers can use different unspec numbers).
;;
;;    HOOK is the gcc-hook object associated with this intrinsic,
;;    or #f if none.
;;
;;    ISAS maps ISA names to the most general implementation of the
;;    intrinsic for that ISA.  Used for error checking.
;; Short-cut functions
;; Return the maximum of HIGHEST and the length of insn property PROPERTY
;; for any implementation of INSTRINSIC.  PROPERTY can the something
;; like MD-INSN:INPUTS or MD-INSN:OUTPUTS.
;; GLOBAL VARIABLES
;; ----------------
;; Maps cgen intrinsic names to intrinsic objects.
;; The list of all intrinsics.  After the analysis phase, this list
;; is in index order.
;; The list of all instructions, in the order they appear in the .md file.
;; When two instructions are compatible, but one is more general than
;; the other, the more general one will come after the less general one.
;; Maps fixed hard registers onto shadow global registers.
;; Create an intrinsic with the given cgen name and gcc hook.  Add it to
;; INTRINSICS and INTRINSIC-TABLE.
;; Return a shadow version of hard register REG.
;; WELL-KNOWN INTRINSICS
;; ---------------------
;; gcc might have a special use for certain intrinsics.  Such intrinsics
;; have a GCC-HOOK structure attached.
;;
;;    RTL-CODE is an rtl code that can be used in the define_insn
;;    pattern instead of usual unspec or unspec_volatile.  Usually
;;    the field is an arithmetic or logic code, but it can also be:
;;
;;        - 'set': the intrinsic implements a move of some sort.
;;        - 'nor': represented in gcc as (and (not X) (not Y)).
;;	  - #f: use unspecs as normal.
;;
;;    CONDITION is a condition that must be true for the RTL-CODE
;;    version of the instruction to be available.
;;
;;    UNSPEC-VERSION is a version of the same intrinsic that has no
;;    gcc-hook structure.  It is sometimes useful to have two versions
;;    of the same instrinsic, one with a specific rtl-code and one
;;    with a general unspec.  The former will allow more optimisations
;;    while the latter will act more like an inline asm statement.
;; Declare a well-known intrinsic with the given cgen name and
;; gcc-hook fields.
;; ANALYSIS PHASE
;; --------------
;; The next available unspec number.
;; Given cgen instruction INSN, return the cgen name of its intrinsic.
"";; Look up an intrinsic by its cgen name.  Create a new intrinsic
;; if the name hasn't been used yet.
;; If instruction INSN assigns to a constant value to OP's field,
;; record it in IFIELD-VALUE.
;; Create an md-insn from the given cgen instruction and add it to MD-INSNS.
;; Create a new md-operand for OP.
;; Find an md-operand for OP, create a new one if we
;; haven't seen it before.
;; A partial order on md-operands.  Sort them by their position
;; in the argument list, putting non-argument operands last.
;;
;; This ordering is needed when non-commutative intrinsics
;; use a specific gcc rtl code.  For example, if we have
;; an intrinsic:
;;
;;      sub (op0, op1, op2)
;;
;; which is known to do subtraction, we might use the MINUS
;; rtl code in the define_insn pattern.  op1 must then be
;; the first input operand and op2 must be the second:
;;
;;      (set op0 (minus op1 op2))
;; Create a version of the broken-out syntax in which
;; each cgen operand is replaced by an md-operand.
;; All relevant outputs.
;; The arguments to the intrinsic function, represented as
;; a list of operands.  Usually this is taken directly from
;; the assembler syntax, but allow machine-specific hacks
;; to modify the list.
;; The operands that we know to be inputs.  For tidiness' sake,
;; remove (pc), which was no real meaning inside an unspec or
;; unspec_volatile.
;; If an argument has not been classified as an input
;; or an output, treat it as an input.  This helps us to
;; deal with insns whose semantics have not been given.
;; Allow an intrinsic to specify a type for coprocessor
;; operands, as they tend to be insn-specific vector types.
;; Number each argument operand according to its position in the list.
;; Sort the inputs and outputs as described above.
;; Assign match_operand numbers to each argument.  Outputs should
;; have lower numbers than inputs.
;; Assign a mode to each operand.  If we have an output operand,
;; use its mode for all immediate operands.  This is mainly for
;; intrinsics which use rtl codes like 'plus': the source operands
;; are then expected to have the same mode as the destination.
;; Make INSN available when generating code for ISA, updating INSN's
;; intrinsic structure accordingly.  Insns are passed to this function
;; in .md file order.
;; We haven't yet seen an implementation of this intrinsic for ISA.
;; The intrinsic has already been implemented for ISA.
;; Check whether INSN is at least as general as the bellwether
;; implementation.  If it isn't, report an error, otherwise
;; use INSN as the new bellwether.
;; This is temporarily disabled as some IVC2 intrinsics *do* have the
;; same actual signature and operands, but different bit encodings
;; depending on the slot.  This different syntax makes them not match.
;;	  (if (not (md-insn:syntax<=? bellwether insn))
;;	      (error (sa "instructions \"" (md-insn:cgen-name insn)
;;			 "\" and \"" (md-insn:cgen-name bellwether)
;;			 "\" are both mapped to intrinsic \""
;;			 (intrinsic:name intrinsic)
;;			 "\" but do not have a compatible syntax")))
;;	  (if (not (md-insn:operands<=? bellwether insn))
;;	      (error (sa "instructions \"" (md-insn:cgen-name insn)
;;			 "\" and \"" (md-insn:cgen-name bellwether)
;;			 "\" are both mapped to intrinsic \""
;;			 (intrinsic:name intrinsic)
;;			 "\" but do not have compatible semantics")))
;; Return true if the given insn should be included in the output files.
"--unused--""--reserved--""--syscall--";; Set up global variables, if we haven't already.
"Analyzing intrinsics...\n";; Set up the global lists.
"cgen_intrinsic_""cgen_intrinsic_unspec_";; Tell each object what position it has in its respective list.
;; Check whether the mapping of instructions to intrinsics is OK.
;; Assign unspec numbers to each intrinsic.
;; ITERATION FUNCTIONS
;; -------------------
;; .MD GENERATOR
;; -------------
;; Write the output template for INSN's define_insn.
;; ??? Still MeP-specific.
"$tp""$sp""%""%l""%"" ""\\\\t";; Write the inputs to INSN, wrapped in an unspec, unspec_volatile,
;; or intrinsic-specific rtl code.  MODE is the mode should go after
;; the wrapper's rtl-code, such as "" or ":SI".  UNSPEC is the unspec
;; number to use, if an unspec is needed, and CONTEXT is as for
;; MD-OPERAND:TO-STRING.
"(unspec_volatile""(unspec"" [""(const_int 0)""] "")""(and"" "")""(not"" "")""("" "")";; Write a "(set ...)" pattern for the given output.  CONTEXT is RHS
;; for the first output and RHS-COPY for the rest.  UNSPEC is an unspec
;; number to use for this output.
"(set "")""(if_then_else "")""(eq "")""""(const_int 0)""(match_dup "")""(pc)"":";; If this instruction is used for expanding intrinsics, and if the
;; output is a fixed register that is not mapped to an intrinsic
;; argument, treat the instruction as setting a global register.
;; This isn't necessary for volatile instructions since gcc will
;; not try to second-guess what they do.
"(set "")""(reg:SI "")"":SI";; Write a define_insn for INSN.
"\n\n(define_insn \"""\"\n""  [""]""";; C predicate.
"  \"CGEN_ENABLE_INSN_P ("")"" && ("")""\"\n";; assembly syntax
"  \"""\"\n";; attributes
"  [""]""(set_attr \"""\" \"""\")"")\n""\n\n"";; DO NOT EDIT: This file is automatically generated by CGEN.\n"";; Any changes you make will be discarded when it is next regenerated.\n""\n\n""Generating .md file...\n";; Define the immediate predicates.
"(define_predicate \"""\"\n""  (and (match_code \"const_int\")\n""        (match_test \"(INTVAL (op) & "") == 0\n""                   && INTVAL (op) >= ""\n""                   && INTVAL (op) < ""\")))\n""\n""\n""";; GCC SOURCE CODE GENERATOR
;; -------------------------
;; Maps the names of immediate predicates to an example of an operand
;; which needs it.
;; If OP is an immediate predicate, make sure that it has an entry
;; in IMMEDIATE-PREDICATES.
"cgen_regnum_operand_type_V8QI""cgen_regnum_operand_type_V4HI""cgen_regnum_operand_type_V2SI""cgen_regnum_operand_type_V8UQI""cgen_regnum_operand_type_V4UHI""cgen_regnum_operand_type_V2USI""cgen_regnum_operand_type_VECTOR""cgen_regnum_operand_type_CP_DATA_BUS_INT""cgen_regnum_operand_type_DI""cgen_regnum_operand_type_SI""cgen_regnum_operand_type_POINTER""cgen_regnum_operand_type_LABEL""cgen_regnum_operand_type_LONG""cgen_regnum_operand_type_ULONG""cgen_regnum_operand_type_SHORT""cgen_regnum_operand_type_USHORT""cgen_regnum_operand_type_CHAR""cgen_regnum_operand_type_UCHAR""cgen_regnum_operand_type_DEFAULT";; Write out the cgen_insn initialiser for INSN.
"  { "" }""ISA""GROUP""CODE_FOR_""1""0""{ "" }""0""{ "" }""{ "", ""{ 0, 0"", "", ""1""0"" }""{ 0, 0, cgen_regnum_operand_type_DEFAULT, 0}"; i.e., mep-intrin.h
"\n\n""/* DO NOT EDIT: This file is automatically generated by CGEN.\n""   Any changes you make will be discarded when it is next regenerated. */\n""\n""Generating gcc include file...\n""#ifdef WANT_GCC_DECLARATIONS\n";; Declare the range of shadow registers
"#define FIRST_SHADOW_REGISTER ""\n""#define LAST_SHADOW_REGISTER ""\n""#define FIXED_SHADOW_REGISTERS \\\n  ""1""\n""#define CALL_USED_SHADOW_REGISTERS FIXED_SHADOW_REGISTERS\n""#define SHADOW_REG_ALLOC_ORDER \\\n  ""\n""#define SHADOW_REGISTER_NAMES \\\n  ""\"$shadow""\"""\n\n";; Declare the index values for well-known intrinsics.
"\n\n#ifndef __MEP__\n""enum {\n""  "" = ""\n};\n""#endif /* ! defined (__MEP__) */\n";; Define the structure used to describe intrinsic insns.
"\n\n""enum cgen_regnum_operand_type {\n""  cgen_regnum_operand_type_POINTER,         /* long *          */\n""  cgen_regnum_operand_type_LABEL,           /* void *          */\n""  cgen_regnum_operand_type_LONG,            /* long            */\n""  cgen_regnum_operand_type_ULONG,           /* unsigned long   */\n""  cgen_regnum_operand_type_SHORT,           /* short           */\n""  cgen_regnum_operand_type_USHORT,          /* unsigned short  */\n""  cgen_regnum_operand_type_CHAR,            /* char            */\n""  cgen_regnum_operand_type_UCHAR,           /* unsigned char   */\n""  cgen_regnum_operand_type_SI,           /* __cop long      */\n""  cgen_regnum_operand_type_DI,           /* __cop long long */\n""  cgen_regnum_operand_type_CP_DATA_BUS_INT, /* cp_data_bus_int */\n""  cgen_regnum_operand_type_VECTOR,		/* opaque vector type */\n""  cgen_regnum_operand_type_V8QI,		/* V8QI vector type */\n""  cgen_regnum_operand_type_V4HI,		/* V4HI vector type */\n""  cgen_regnum_operand_type_V2SI,		/* V2SI vector type */\n""  cgen_regnum_operand_type_V8UQI,		/* V8UQI vector type */\n""  cgen_regnum_operand_type_V4UHI,		/* V4UHI vector type */\n""  cgen_regnum_operand_type_V2USI,		/* V2USI vector type */\n""  cgen_regnum_operand_type_DEFAULT = cgen_regnum_operand_type_LONG\n""};\n""\n""struct cgen_regnum_operand {\n""  /* The number of addressable registers, 0 for non-regnum operands.  */\n""  unsigned char count;\n""\n""  /* The first register.  */\n""  unsigned char base;\n""\n""  /* The type of the operand.  */\n""  enum cgen_regnum_operand_type type;\n""\n""  /* Is it passed by reference?  */\n""  int reference_p;\n""};\n\n""struct cgen_insn {\n""  /* An index into cgen_intrinsics[].  */\n""  unsigned int intrinsic;\n""\n""  /* A bitmask of the ISAs which include this instruction.  */\n""  unsigned int isas;\n""\n""  /* A bitmask of the target-specific groups to which this instruction\n""     belongs.  */\n""  unsigned int groups;\n""\n""  /* The insn_code for this instruction.  */\n""  int icode;\n""\n""  /* The number of arguments to the intrinsic function.  */\n""  unsigned int num_args;\n""\n""  /* If true, the first argument is the return value.  */\n""  unsigned int cret_p;\n""\n""  /* Maps operand numbers to argument numbers.  */\n""  unsigned int op_mapping[10];\n""\n""  /* Array of regnum properties, indexed by argument number.  */\n""  struct cgen_regnum_operand regnums[10];\n""};\n";; Declare the arrays that we define later.
"\n""extern const struct cgen_insn cgen_insns[];\n""extern const char *const cgen_intrinsics[];\n";; Macro used by the .md file.
"\n""/* Is the instruction described by cgen_insns[INDEX] enabled?  */\n""#define CGEN_ENABLE_INSN_P(INDEX) \\\n""  ((CGEN_CURRENT_ISAS & cgen_insns[INDEX].isas) != 0 \\\n""   && (CGEN_CURRENT_GROUP & cgen_insns[INDEX].groups) != 0)\n\n""ISA""GROUP""#endif\n""#ifdef WANT_GCC_DEFINITIONS\n";; Create an array describing the range and alignment of immediate
;; predicates.
"struct cgen_immediate_predicate {\n""  insn_operand_predicate_fn predicate;\n""  int lower, upper, align;\n""};\n\n""const struct cgen_immediate_predicate cgen_immediate_predicates[] = {\n""  { "", "", "", "" }""\n};\n\n";; Create an array containing the names of all the available intrinsinics.
"const char *const cgen_intrinsics[] = {\n""  \"""\"""\n};\n\n";; Create an array describing each .md file instruction.
"const struct cgen_insn cgen_insns[] = {\n""\n};\n""#endif\n";; PROTOTYPE GENERATOR
;; -------------------
"long *""void *""long""unsigned long""short""unsigned short""char""unsigned char";;(logit 0 "op " (md-operand:cdata op) " cptype " cptype "\n")
"cp_v2si""cp_v4hi""cp_v8qi""cp_v2usi""cp_v4uhi""cp_v8uqi""cp_vector""cp_data_bus_int""long""*"""; i.e., intrinsics.h
"\n\n""/* DO NOT EDIT: This file is automatically generated by CGEN.\n""   Any changes you make will be discarded when it is next regenerated.\n""*/\n\n""/* GCC defines these internally, as follows... \n";
"#if __MEP_CONFIG_CP_DATA_BUS_WIDTH == 64\n""  typedef long long cp_data_bus_int;\n""#else\n""  typedef long cp_data_bus_int;\n""#endif\n""typedef          char  cp_v8qi  __attribute__((vector_size(8)));\n""typedef unsigned char  cp_v8uqi __attribute__((vector_size(8)));\n""typedef          short cp_v4hi  __attribute__((vector_size(8)));\n""typedef unsigned short cp_v4uhi __attribute__((vector_size(8)));\n""typedef          int   cp_v2si  __attribute__((vector_size(8)));\n""typedef unsigned int   cp_v2usi __attribute__((vector_size(8)));\n""*/\n\n""Generating prototype file...\n""\n// ""\n""void"" "" ("", "");""volatile""// "" ""\n""";; The rest of this file has not been converted to use the INTRINSICS
;; attribute.  The code isn't used at the moment anyway.
"\n""""7""&&lab""0x"""""" + 1""p""l""ul""s""us""c""uc""cpdbi""l"""", ""x""y""z""t""w""--unused--""--reserved--"" ("");\n"