Subversion Repositories scarts

; CPU architecture description.
; Copyright (C) 2000, 2003, 2009 Red Hat, Inc.
; This file is part of CGEN.
; See file COPYING.CGEN for details.
; Top level class that records everything about a cpu.
; FIXME: Rename this to something else and rename <arch-data> to <arch>
; for consistency with other classes (define-foo -> <foo> object).
; An object of type <arch-data>.
;; ??? All should really be assumed to be a black-box table.
; FIXME: wip (and move elsewhere)
; FIXME: wip (and move elsewhere)
; standard values derived from the input data
; #t if instructions have been analyzed
; #t if semantics were included in the analysis
; #t if alias insns were included in the analysis
; ordinal of next object that needs one
; Accessors.
; Each getter is arch-foo.
; Each setter is arch-set-foo!.
; For elements recorded as a table, return a sorted list.
; ??? All elements should really be assumed to be a black-box table.
;; Get the next ordinal and increment it for the next time.
;; FIXME: temp hack for current-ifld-lookup, current-op-lookup.
;; Return the element of list L with the lowest ordinal.
;; Table of <source-ident> objects with two access styles:
;; hash lookup, ordered list.
;; The main table is the hash table, the list is lazily created and cached.
;; The table is recorded as (hash-table . list).
;; The list is #f if it needs to be computed.
;; Each entry in the hash table is a list, multiple objects can have the same
;; key (e.g. insns from different isas can have the same name).
;;
;; This relies on the ordinal element of <source-ident> objects to build the
;; ordered list.
;; Return ordered list.
;;
;; To allow splicing in new objects we recognize two kinds of ordinal numbers:
;; integer and (integer . integer) where the latter is a pair of
;; major-ordinal-number and minor-ordinal-number.
;; NOTE: {value} usually contains just
;; one element.
;; Ordinals are either an integer or
;; (major . minor).
;; Quick test for common case.
;; Add an entry to an ident-object-table.
;; Give OBJECT an ordinal if it doesn't have one already.
;; Remember: Elements in the hash table are lists of objects, this is because
;; multiple objects can have the same key if they come from different isas.
;; Need to recompute the sorted list.
;; Look up KEY in an ident-object-table.
; Class for recording things specified in `define-arch'.
; This simplifies define-arch as the global arch object CURRENT-ARCH
; must exist before loading the .cpu file.
; Default alignment of memory operations.
; One of aligned, unaligned, forced.
; Orientation of insn bit numbering (#f->msb=0, #t->lsb=0).
; List of all machs.
; Each element is pair of (mach-name . sanitize-key)
; where sanitize-key is #f if there is none.
; blah blah blah ... ooohhh, evil sanitize key, blah blah blah
; List of all isas (instruction set architecture).
; Each element is a pair of (isa-name . sanitize-key)
; where sanitize-key is #f if there is none.
; There is usually just one.  ARM has two (arm, thumb).
; blah blah blah ... ooohhh, evil sanitize key, blah blah blah
; ??? Defaults for other things should be here.
; Add, list, lookup accessors for <arch>.
;
; For the lookup routines, the result is the object or #f if not found.
; For some, if X is already an object, return that.
; Attributes.
; Recorded as a pair of lists.
; The car is a list of <attribute> objects.
; The cdr is an associative list of (name . <attribute>) elements, for lookup.
; Could use a hash table except that there currently aren't that many.
; NOTE: While putting this test in define-attr feels better, having it here
; is more robust, internal calls get checked too.  Thus it's here.
; Ditto for all the other such tests in this file.
"define-attr""attribute already defined"; Build list in normal order so we don't have to reverse it at the end
; (since our format is non-trivial).
; Enums.
"define-enum""enum already defined"; Keywords.
"define-keyword""keyword already defined"; Instruction sets.
"define-isa""isa already defined"; Cpu families.
"define-cpu""cpu already defined"; Machines.
"define-mach""mach already defined"; Models.
"define-model""model already defined"; Hardware elements.
"define-hardware""hardware already defined"; This doesn't use object-assq on purpose.  Hardware objects handle
; get-name specially.
; Instruction fields.
"define-ifield""ifield already defined";; Look up ifield X in the current architecture.
;;
;; If X is an <ifield> object, just return it.
;; This is to handle ???
;; Otherwise X is the name of the ifield to look up.
;;
;; ??? This doesn't work if there are multiple operands with the same name
;; for different isas.
;; FIXME: For now just return the first one,
;; same behaviour as before.
;; Here "first one" means "first defined".
; Return a boolean indicating if <ifield> F is currently defined.
; This is slightly complicated because multiple isas can have different
; ifields with the same name.
; We've got all the ifields with the same name,
; now see if any have the same ISA as F.
; Operands.
"define-operand""operand already defined"; ??? This doesn't work if there are multiple operands with the same name
; for different isas.
;; FIXME: For now just return the first one, same behaviour as before.
;; Here "first one" means "first defined".
; Return a boolean indicating if <operand> OP is currently defined.
; This is slightly complicated because multiple isas can have different
; operands with the same name.
; We've got all the operands with the same name,
; now see if any have the same ISA as OP.
; Instruction field formats.
; Semantic formats (akin to ifmt's, except includes semantics to distinguish
; insns).
; Instructions.
"define-insn""insn already defined"; ??? This doesn't work if there are multiple insns with the same name
; for different isas.
;; FIXME: For now just flag an error.
;; Later add an isa-list arg to distinguish.
"multiple insns with name:"; Return a boolean indicating if <insn> INSN is currently defined.
; This is slightly complicated because multiple isas can have different
; insns with the same name.
; We've got all the insns with the same name,
; now see if any have the same ISA as INSN.
; Macro instructions.
"define-minsn""macro-insn already defined"; ??? This doesn't work if there are multiple minsns with the same name
; for different isas.
;; FIXME: For now just flag an error.
;; Later add an isa-list arg to distinguish.
"multiple macro-insns with name:"; Return a boolean indicating if <macro-insn> MINSN is currently defined.
; This is slightly complicated because multiple isas can have different
; macro-insns with the same name.
; We've got all the macro-insns with the same name,
; now see if any have the same ISA as M.
; rtx subroutines.
"define-subr""subroutine already defined"; Arch parsing support.
; Parse an alignment spec.
"invalid alignment"; Parse an arch mach spec.
; The value is a list of mach names or (mach-name sanitize-key) elements.
; The result is a list of (mach-name . sanitize-key) elements.
; ok
"bad arch mach spec"; Parse an arch isa spec.
; The value is a list of isa names or (isa-name sanitize-key) elements.
; The result is a list of (isa-name . sanitize-key) elements.
; ok
"bad arch isa spec"; Parse an architecture description
; This is the main routine for building an arch object from a cpu
; description in the .cpu file.
; All arguments are in raw (non-evaluated) form.
"Processing arch "" ...\n""arch"; Read an architecture description.
; This is the main routine for analyzing an arch description in the .cpu file.
; ARG-LIST is an associative list of field name and field value.
; parse-arch is invoked to create the `arch' object.
"arch-read"; <arch-data> object members and default values
"unknown"""; Loop over each element in ARG-LIST, recording what's found.
"invalid arch arg"; Ensure required fields are present.
"missing machs spec""missing isas spec"; Now that we've identified the elements, build the object.
; Define an arch object, name/value pair list version.
; Install the builtin objects now that we have an arch, and now that
; attributes MACH and ISA exist.
; Mach/isa processing.
; Create the MACH attribute.
; MACHS is the canonicalized machs spec to define-arch: (name . sanitize-key).
"machine type selection"; Return #t if MACH is supported by OBJ.
; This is done by looking for the MACH attribute in OBJ.
; By definition, objects that support the default (base) mach support
; all machs.
;(let ((deflt (attr-lookup-default 'MACH obj)))
;  (any-true? (map (lambda (m) (memq m deflt)) machs)))))
; Create the ISA attribute.
; ISAS is the canonicalized isas spec to define-arch: (name . sanitize-key).
; ISAS is a list of isa names.
; Using a bitset attribute here implies something could be used by two
; separate isas.  This seems highly unlikely but we don't [as yet]
; preclude it.  The other thing to consider is whether the cpu table
; would ever want to be opened for multiple isas.
"instruction set selection"; If there's only one isa, don't (yet) pollute the tables with a value
; for it.
; Return the bitset attr value for all isas.
","; Return an ISA attribute of all isas.
; This is useful for things like f-nil which exist across all isas.
; Return list of ISA names specified by attribute object ATLIST.
; Return list of ISA names specified by OBJ.
; Return #t if <isa> ISA is supported by OBJ.
; This is done by looking for the ISA attribute in OBJ.
; The fetch/decode/execute process.
; "extract" is a fancy word for fetch/decode.
; FIXME: wip, not currently used.
; FIXME: move to inside define-isa, and maybe elsewhere.
;
;(defmacro
;  define-extract (code)
;  ;(arch-set-insn-extract! CURRENT-ARCH code)
;  *UNSPECIFIED*
;)
;
;(defmacro
;  define-execute (code)
;  ;(arch-set-insn-execute! CURRENT-ARCH code)
;  *UNSPECIFIED*
;)
; ISA specification.
; Each architecture is generally one isa, but in the case of ARM (and a few
; others) there is more than one.
;
; ??? "ISA" has a very well defined meaning, and our usage of it one might
; want to quibble over.  A better name would be welcome.
; Associated with an instruction set is its framing.
; This refers to how instructions are laid out at the liw level (where several
; insns are framed together and executed sequentially or in parallel).
; ??? If one defines the term "format" as being how an individual instruction
; is laid out then formatting can be thought of as being different from
; framing.  However, it's possible for a particular ISA to intertwine the two.
; Thus this will need to evolve.
; ??? Not used yet, wip.
; pronounced I-frame
; list of <itype> objects that make up the frame
; assembler syntax
; list of (length value) elements that make up the format
; Length is in bits.  Value is either a number or a $number
; symbol refering to the insn specified in `insns'.
; Initial bitnumbers to decode insns by.
; ??? At present the rest of the decoding is determined
; algorithmically.  May wish to give the user more control
; [like psim].
; rtl that executes instructions in `value'
; Fields specified in `value' can be used here.
; Accessors.
; Instruction types, recorded in <iframe>.
; ??? Not used yet, wip.
; length in bits, or initial part if variable length (wip)
; constraint specifying which insns are included
; Initial bitnumbers to decode insns by.
; ??? At present the rest of the decoding is determined
; algorithmically.  May wish to give the user more control
; [like psim].
; Accessors.
; Simulator instruction decode splitting.
; FIXME: Should live in simulator specific code.  Requires class handling
; cleanup first.
;
; Instructions can be split by particular values for an ifield.
; The ARM port uses this to split insns into those that set the pc and
; those that don't.
; Name of ifield to split on.
; Constraint.  Only insns satifying this constraint are
; split.  #f if no constraint.
; List of ifield splits.
; Each element is one of (name value) or (name (values)).
; Accessors.
; Parse a decode-split spec.
; SPEC is (ifield-name constraint value-list).
; CONSTRAINT is an rtl expression.  Only insns satifying the constraint
; are split.
; Each element of VALUE-LIST is one of (name value) or (name (values)).
; FIXME: All possible values must be specified.  Need an `else' clause.
; Ranges would also be useful.
"decode-split spec is (ifield-name constraint value-list)"; FIXME: more error checking.
; Parse a list of decode-split specs.
; Top level class to describe an isa.
; Default length to record in ifields.
; This is used in calculations involving bit numbers.
; Length of an unknown instruction.  Used by disassembly
; and by the simulator's invalid insn handler.
; Number of bytes of insn that can be initially fetched.
; In non-LIW isas this would be the length of the smallest
; insn.  For LIW isas it depends - only one LIW isa is
; currently supported (m32r).
; Initial bitnumbers to decode insns by.
; ??? At present the rest of the decoding is determined
; algorithmically.  May wish to give the user more control
; [like psim].
; Number of instructions that can be fetched at a time
; [e.g. 2 on m32r].
; Maximum number of instructions the cpu can execute in
; parallel.
; FIXME: Rename to max-parallel-insns.
; List of <iframe> objects.
;frames
; Condition tested before execution of any instruction or
; #f if there is none.  For architectures like ARM, ARC.
; If specified it is a pair of
; (condition-field-name . rtl-for-condition)
; Code to execute after CONDITION and prior to SEMANTICS.
; This is rtl in source form or #f if there is none.
; This is generally unused.  It is used on the ARM to set
; R15 to the correct value.
; The reason it's not specified with SEMANTICS is that it is
; believed some applications won't need/want this.
; ??? It is a bit of a hack though, as it is used to aid
; implementation of apps (e.g. simulator).  Arguably something
; that doesn't belong here.  Maybe as more architectures are
; ported that have the PC as a general register, a better way
; to do this will arise.
; list of simulator instruction splits
; FIXME: should live in simulator file (needs class cleanup).
; ??? More may need to migrate here.
; Accessors.
"ISA_"; Return minimum/maximum size in bits of all insns in the isa.
; add `65535' in case list is nil (avoids crash)
; [a language with infinite precision can't have min-reduce-iota-0 :-)]
; add `0' in case list is nil (avoids crash)
; [a language with infinite precision can't have max-reduce-iota-0 :-)]
; Return a boolean indicating if instructions in ISA can be kept in a
; portable int.
; Parse an isa condition spec.
; `condition' here refers to the condition performed by architectures like
; ARM and ARC before each insn.
"condition spec not `(ifield-name rtl-code)'"; Parse a setup-semantics spec.
; Parse an isa spec.
; The result is the <isa> object.
; All arguments are in raw (non-evaluated) form.
"Processing isa "" ...\n";; Pick out name first to augment the error context.
"isa name is not present in `define-arch'"; Isa's are always kept - we need them to validate later uses, even if
; the then resulting object won't be kept.  All isas are also needed to
; compute a proper value for the isas-cache member of <hardware-base>
; for builtin objects.
"isa"": default-insn-word-bitsize"": default-insn-bitsize"": base-insn-bitsize"; Read an isa entry.
; ARG-LIST is an associative list of field name and field value.
"";; FIXME: Hobbit computes the wrong symbol for `parallel-insns'
;; in the `case' expression below because there is a local var
;; of the same name ("__1" gets appended to the symbol name).
; ignore for now
; ignore for now
"invalid isa arg";; Now that we've identified the elements, build the object.
; Define a <isa> object, name/value pair list version.
"define-isa"; Subroutine of modify-isa to process one add-decode-split spec.
; Main routine for modifying existing isa definitions
"modify-isa""isa name not specified""undefined isa"; done
; ignore, already processed
"invalid/unsupported option"; Return boolean indicating if ISA supports parallel execution.
; Return a boolean indicating if ISA supports conditional execution
; of all instructions.
; The `<cpu>' object collects together various details about a particular
; subset of the architecture (e.g. perhaps all 32 bit variants of the sparc
; architecture).
; This is called a "cpu-family".
; ??? May be renamed to <family> (both internally and in the .cpu file).
; ??? Another way to do this would be to discard the family notion and allow
; machs to inherit from other machs, as well as use isas to distinguish
; sufficiently dissimilar machs.  This would remove a fuzzy illspecified
; notion with a concrete one.
; ??? Maybe a better way to organize sparc32 vs sparc64 is via an isa.
; one of big/little/either/#f.
; If #f, then {insn,data,float}-endian are used.
; Otherwise they're ignored.
; one of big/little/either.
; one of big/little/either/big-words/little-words.
; If big-words then each word is little-endian.
; If little-words then each word is big-endian.
; one of big/little/either/big-words/little-words.
; number of bits in a word.
; number of bits in a chunk of an instruction word, for
; endianness conversion purposes; 0 = no chunking
; Transformation to use in generated files should one be
; needed.  At present the only supported value is a string
; which is the file suffix.
; ??? A dubious element of the description language, but given
; the quantity of generated files, some machine generated
; headers may need to #include other machine generated headers
; (e.g. cpuall.h).
; Allow a cpu family to override the isa parallel-insns spec.
; ??? Concession to the m32r port which can go away, in time.
; Computed: maximum number of insns which may pass before there
; an insn writes back its output operands.
; Accessors.
; Return endianness of instructions.
; Return endianness of data.
; Return endianness of floats.
; Parse a cpu family description
; This is the main routine for building a <cpu> object from a cpu
; description in the .cpu file.
; All arguments are in raw (non-evaluated) form.
"Processing cpu family "" ...\n";; Pick out name first to augment the error context.
"cpu"; default max-delay. will compute correct value
"Ignoring "".\n"; cpu is not to be kept
; Read a cpu family description
; This is the main routine for analyzing a cpu description in the .cpu file.
; CONTEXT is a <context> object for error messages.
; ARG-LIST is an associative list of field name and field value.
; -cpu-parse is invoked to create the <cpu> object.
"";; FIXME: Hobbit computes the wrong symbol for `parallel-insns'
;; in the `case' expression below because there is a local var
;; of the same name ("__1" gets appended to the symbol name).
;; Loop over each element in ARG-LIST, recording what's found.
"invalid cpu arg";; Now that we've identified the elements, build the object.
; Define a cpu family object, name/value pair list version.
"define-cpu"; The `<mach>' object describes one member of a `cpu' family.
; cpu family this mach is a member of
; bfd name of mach
; list of <isa> objects
; Accessors.
"MACH_"; Parse a machine entry.
; The result is a <mach> object or #f if the mach isn't to be kept.
; All arguments are in raw (non-evaluated) form.
"Processing mach "" ...\n";; Pick out name first to augment the error context.
"isa spec not a list""mach name is not present in `define-arch'""missing cpu spec""unknown cpu""missing isas spec""unknown isa in""bfd-name not a string""mach""Ignoring "".\n"; mach is not to be kept
; Read a mach entry.
; CONTEXT is a <context> object for error messages.
; ARG-LIST is an associative list of field name and field value.
"invalid mach arg";; Now that we've identified the elements, build the object.
;; Default bfd-name is same as object's name.
;; Default isa is the first one.
; Define a <mach> object, name/value pair list version.
"define-mach"; Miscellaneous state derived from the input data.
; FIXME: being redone
; Size of a word in bits.
; All selected cpu families must have same value or error.
; Ergo, don't use this if multiple word-bitsize values are expected.
; E.g. opcodes support for architectures with both 32 and 64 variants.
"multiple word-bitsize values"; Return maximum word bitsize.
; Size of normal instruction.
; All selected isas must have same value or error.
; FIXME: ensure all have same value.
; Number of bytes of insn we can initially fetch.
; All selected isas must have same value or error.
; FIXME: ensure all have same value.
; Return parallel-insns spec.
; Assert only one cpu family has been selected.
; ??? The m32r does have parallel execution, but to keep support for the
; base mach simpler, a cpu family is allowed to override the isa spec.
; FIXME: ensure all have same value.
; Return boolean indicating if parallel execution support is required.
; Return liw-insns spec.
; FIXME: ensure all have same value.
; Return decode-assist spec.
; Return boolean indicating if current isa conditionally executes all insn.
; Architecture or cpu wide values derived from other data.
; whether all insns can be recorded in a host int
; Called after the .cpu file has been read in to prime derived value
; computation.
; Often this data isn't needed so we only computed it if we have to.
; Don't compute this data unless we need to.
; integral-insn?
; Accessors.
; Instruction analysis control.
;; The maximum number of virtual insns.
;; They can be recorded with negative ordinals, and multi-insns are currently
;; also recorded as negative numbers, so leave enough space.
; Analyze the instruction set.
; The name is explicitly vague because it's intended that all insn analysis
; would be controlled here.
; If the instruction set has already been sufficiently analyzed, do nothing.
; INCLUDE-ALIASES? is #t if alias insns are to be included.
; ANALYZE-SEMANTICS? is #t if insn semantics are to be analyzed.
;
; This is a very expensive operation, so we only do it as necessary.
; There are (currently) two different kinds of users: assemblers and
; simulators.  Assembler style apps don't always need to analyze the semantics.
; Simulator style apps don't want to include the alias insns.
; Catch apps that haven't set word sizes yet.
;; FIXME: This shouldn't be calling current-insn-list,
;; it should use (arch-insn-list arch).
;; Then again various subroutines assume arch == CURRENT-ARCH.
;; Still, something needs to be cleaned up.
; Instantiate sub-insns of all multi-insns.
"Instantiating multi-insns ...\n";; FIXME: Hack to remove differences in generated code when we
;; switched to recording insns in hash tables.
;; Multi-insn got instantiated after the list of insns had been
;; reversed and they got added to the front of the list, in
;; reverse order.  Blech!
;; Eventually remove this, have a flag day, and check in the
;; updated files.
;; NOTE: This causes major diffs to opcodes/m32c-*.[ch].
; This is expensive so indicate start/finish.
"Analyzing instruction set ...\n""Done analysis.\n"; Called before a .cpu file is read in.
"\
Define an architecture, name/value pair list version.
""\
Define an instruction set architecture, name/value pair list version.
""\
Modify an isa, name/value pair list version.
""\
Define a cpu family, name/value pair list version.
"; Called before a .cpu file is read in.
"\
Define a machine, name/value pair list version.
"; Called after .cpu file is read in.
; Lists are constructed in the reverse order they appear in the file
; [for simplicity and efficiency].  Restore them to file order for the
; human reader/debugger.
; We don't need to do this for ifld, op, insn, minsn lists because
; they are handled differently.
; Called after .cpu file is read in.