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; Decoder generation.
; Copyright (C) 2000, 2001, 2009 Red Hat, Inc.
; This file is part of CGEN.
; Names of various global vars.
; Name of insn descriptor table var.
"@prefix@_insn_data"; Return decode entries for each insn.
; ??? At one point we generated one variable per instruction rather than one
; big array.  It doesn't matter too much (yet).  Generating one big array is
; simpler.
; Print the higher detailed stuff at higher verbosity.
"Processing decode insn globals ...\n""\
/* Insn can't be executed in parallel.
   Or is that \"do NOt Pass to Air defense Radar\"? :-) */
#define NOPAR (-1)
\n""""\
/* The instruction descriptor array.
   This is computed at runtime.  Space for it is not malloc'd to save a
   teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
   but won't be done until necessary (we don't currently support the runtime
   addition of instructions nor an SMP machine with different cpus).  */
static IDESC ""[@PREFIX@_INSN__MAX];
 
/* Commas between elements are contained in the macros.
   Some of these are conditionally compiled out.  */
 
static const struct insn_sem @prefix@_insn_sem[] =
{\n""  { ""VIRTUAL_INSN_"", ""@ARCH@_INSN_"", ""@PREFIX@_INSN_"", ""@PREFIX@_"", @PREFIX@_INSN_PAR_"", ""@PREFIX@_INSN_READ_""@PREFIX@_INSN_WRITE_"", NOPAR, NOPAR """" },\n""\
};
 
static const struct insn_sem @prefix@_insn_sem_invalid = {
  VIRTUAL_INSN_X_INVALID, @PREFIX@_INSN_X_INVALID, @PREFIX@_SFMT_EMPTY"", NOPAR, NOPAR""""
};
\n"; Return enum name of format FMT.
; Generate decls for the insn descriptor table type IDESC.
"\
extern const IDESC *@prefix@_decode (SIM_CPU *, IADDR,
                                  CGEN_INSN_INT,"" CGEN_INSN_INT,\n""\n""\
                                  ARGBUF *);
extern void @prefix@_init_idesc_table (SIM_CPU *);
extern void @prefix@_sem_init_idesc_table (SIM_CPU *);
extern void @prefix@_semf_init_idesc_table (SIM_CPU *);
\n"; Return definition of C function to initialize the IDESC table.
; @prefix@_init_idesc_table is defined here as it depends on with-parallel?
; and thus can't be defined in sim/common.
"\
/* Initialize an IDESC from the compile-time computable parts.  */
 
static INLINE void
init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
{
  const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
 
  id->num = t->index;
  id->sfmt = t->sfmt;
  if ((int) t->type <= 0)
    id->idata = & cgen_virtual_insn_table[- (int) t->type];
  else
    id->idata = & insn_table[t->type];
  id->attrs = CGEN_INSN_ATTRS (id->idata);
  /* Oh my god, a magic number.  */
  id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
 
#if WITH_PROFILE_MODEL_P
  id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
  {
    SIM_DESC sd = CPU_STATE (cpu);
    SIM_ASSERT (t->index == id->timing->num);
  }
#endif
 
  /* Semantic pointers are initialized elsewhere.  */
}
 
/* Initialize the instruction descriptor table.  */
 
void
@prefix@_init_idesc_table (SIM_CPU *cpu)
{
  IDESC *id,*tabend;
  const struct insn_sem *t,*tend;
  int tabsize = @PREFIX@_INSN__MAX;
  IDESC *table = "";
 
  memset (table, 0, tabsize * sizeof (IDESC));
 
  /* First set all entries to the `invalid insn'.  */
  t = & @prefix@_insn_sem_invalid;
  for (id = table, tabend = table + tabsize; id < tabend; ++id)
    init_idesc (cpu, id, t);
 
  /* Now fill in the values for the chosen cpu.  */
  for (t = @prefix@_insn_sem, tend = t + sizeof (@prefix@_insn_sem) / sizeof (*t);
       t != tend; ++t)
    {
      init_idesc (cpu, & table[t->index], t);\n""\
      if (t->par_index != NOPAR)
	{
	  init_idesc (cpu, &table[t->par_index], t);
	  table[t->index].par_idesc = &table[t->par_index];
	}\n""""\
      if (t->par_index != NOPAR)
	{
	  init_idesc (cpu, &table[t->write_index], t);
	  table[t->par_index].par_idesc = &table[t->write_index];
	}\n""""\
    }
 
  /* Link the IDESC table into the cpu.  */
  CPU_IDESC (cpu) = table;
}
 
"; Instruction field extraction support.
; Two implementations are provided, one for !with-scache and one for
; with-scache.
;
; Extracting ifields is a three phase process.  First the ifields are
; extracted and stored in local variables.  Then any ifields requiring
; additional processing for operands are handled.  Then in the with-scache
; case the results are stored in a struct for later retrieval by the semantic
; code.
;
; The !with-scache case does this processing in the semantic function,
; except it doesn't need the last step (it doesn't need to store the results
; in a struct for later use).
;
; The with-scache case extracts the ifields in the decode function.
; Furthermore, we use <sformat-argbuf> to reduce the quantity of structures
; created (this helps semantic-fragment pbb engines).
; Return C code to record <ifield> F for the semantic handler
; in a local variable rather than an ARGBUF struct.
"  "" = "";\n"; Return three of arguments to TRACE:
; string argument to fprintf, character indicating type of third arg, value.
; The type is one of: x.
; FIXME: Add method to return fprintf format string.
", \""" 0x%x\""", 'x'"", "; Instruction field extraction support cont'd.
; Hardware support.
; gen-extract method.
; For the default case we use the ifield as is, which is output elsewhere.
""; gen-trace-extract method.
; Return appropriate arguments for TRACE_EXTRACT.
""; Extract the necessary fields into ARGBUF.
"  "" = & "";\n"""; Return appropriate arguments for TRACE_EXTRACT.
; FIXME: Add method to return fprintf format string.
", \""" 0x%x\""", 'x'"", """; Extract the necessary fields into ARGBUF.
"  "" = "";\n"; Return appropriate arguments for TRACE_EXTRACT.
; FIXME: Add method to return fprintf format string.
", \""" 0x%x\""", 'x'"", "; Instruction field extraction support cont'd.
; Operand support.
; Return C code to record the field for the semantic handler.
; In the case of a register, this is usually the address of the register's
; value (if CACHE-ADDR).
; LOCAL? indicates whether to record the value in a local variable or in
; the ARGBUF struct.
; ??? Later allow target to provide an `extract' expression.
; Return three of arguments to TRACE_EXTRACT:
; string argument to fprintf, character indicating type of third arg, value.
; The type is one of: x.
; Return C code to define local vars to hold processed ifield data for
; <sformat> SFMT.
; This is used when !with-scache.
; Definitions of the extracted ifields is handled elsewhere.
"  "" "";\n"""; Return C code to assign values to the local vars that hold processed ifield
; data for <sformat> SFMT.
; This is used when !with-scache.
; Assignment of the extracted ifields is handled elsewhere.
; Instruction field extraction support cont'd.
; Emit extraction section of decode function.
; Return C code to record insn field data for <sformat> SFMT.
; This is used when with-scache.
"  /* Record the fields for the semantic handler.  */\n""  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, ""\"""\""", (char *) 0));\n"; Return C code to record insn field data for profiling.
; Also recorded are operands not mentioned in the fields but mentioned
; in the semantic code.
;
; FIXME: Register usage may need to be tracked as an array of longs.
; If there are more than 32 regs, we can't know which until build time.
; ??? For now we only handle reg sets of 32 or less.
;
; ??? The other way to obtain register numbers is to defer computing them
; until they're actually needed.  It will speed up execution when not doing
; profiling, though the speed up is only for the extraction phase.
; On the other hand the current way has one memory reference per register
; number in the profiling routines.  For RISC this can be a lose, though for
; more complicated instruction sets it could be a win as all the computation
; is kept to the extraction phase.  If someone wants to put forth some real
; data, this might then be changed (or at least noted).
"""#if WITH_PROFILE_MODEL_P\n""  /* Record the fields for profiling.  */\n""  if (PROFILE_MODEL_P (current_cpu))\n""    {\n""    }\n""#endif\n"; Return C code that extracts the fields of <sformat> SFMT.
;
; Extraction is based on formats to reduce the amount of code generated.
; However, we also need to emit code which records the hardware elements used
; by the semantic code.  This is currently done by recording this information
; with the format.
"Processing extractor for \"""\" ...\n"" extract_"":\n""  {\n""    const IDESC *idesc = &""[itype];\n""    CGEN_INSN_INT insn = ""entire_insn;\n""base_insn;\n""""    ""\n""    ""\n""\n""    return idesc;\n""  }\n\n"; For each format, return its extraction function.
"Processing extractors ...\n"; Generate top level decoder.
; INITIAL-BITNUMS is a target supplied list of bit numbers to use to
; build the first decode table.  If nil, we compute 8 bits of it (FIXME)
; ourselves.
; LSB0? is non-#f if bit number 0 is the least significant bit.
; Compute the initial DECODE-BITSIZE as the minimum of all insn lengths.
; The caller of @prefix@_decode must fetch and pass exactly this number of bits
; of the instruction.
; ??? Make this a parameter later but only if necessary.
; Compute INITIAL-BITNUMS if not supplied.
; 0 is passed for the start bit (it is independent of lsb0?)
; startbit
; max
; All set.  gen-decoder does the hard part, we just print out the result. 
"    ""\
/* Given an instruction, return a pointer to its IDESC entry.  */
 
const IDESC *
@prefix@_decode (SIM_CPU *current_cpu, IADDR pc,
              CGEN_INSN_INT base_insn,"" CGEN_INSN_INT entire_insn,\n""\n""\
              ARGBUF *abuf)
{
  /* Result of decoder.  */
  @PREFIX@_INSN_TYPE itype;
 
  {
    CGEN_INSN_INT insn = base_insn;
\n""\
  }
\n""\
  /* The instruction has been decoded, now extract the fields.  */\n\n"; Without the scache, extraction is defered until the semantic code.
"\
  /* Extraction is defered until the semantic code.  */
 
 done:
  return &""[itype];\n""\
}\n"; Entry point.  Generate decode.h.
"Generating ""'s decode.h ...\n"; Turn parallel execution support on if cpu needs it.
"Decode header for @prefix@.""\
#ifndef @PREFIX@_DECODE_H
#define @PREFIX@_DECODE_H
 
""#endif /* @PREFIX@_DECODE_H */\n"; Entry point.  Generate decode.c.
"Generating ""'s decode.c ...\n"; Turn parallel execution support on if cpu needs it.
; Tell the rtx->c translator we are the simulator.
"Simulator instruction decoder for @prefix@.""\
#define WANT_CPU @cpu@
#define WANT_CPU_@CPU@
 
#include \"sim-main.h\"
#include \"sim-assert.h\"\n\n"