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; SCARTS 16-bit architecture variant description.  -*- Scheme -*-
; Copyright 2000, 2001 Free Software Foundation, Inc.
; Contributed by Martin Walter <mwalter@opencores.org>
;
; This file is part of the GNU Binutils.
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 2 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
;

(include "simplify.inc")

;---------------------------
; Architectural Definitions 
;---------------------------

(define-arch
  (name scarts_16)
  (comment "SCARTS (16-bit architecture variant)")
  (default-alignment aligned)
  (insn-lsb0? #t)
  (machs scarts_16)
  (isas scarts_16)
)

; Instruction set parameters
(define-isa
  (name scarts_16)
  (comment "SCARTS (16-bit architecture variant) instruction set architecture")

  ; Instructions are always 16 bits wide.
  (default-insn-word-bitsize 16)
  (default-insn-bitsize 16)
  (base-insn-bitsize 16)
)

; CPU familiy definitions
(define-cpu
  ; CPU names must be distinct from the architecture name and machine names.
  ; The "b" suffix stands for "base" and is the convention.
  ; The "f" suffix stands for "family" and is the convention.
  (name scarts_16bf)
  (comment "SCARTS (16-bit architecture variant) CPU base family")
  (endian little)
  (word-bitsize 16)
)

; CPU variant (machine) definitions
(define-mach
  (name scarts_16)
  (comment "SCARTS (16-bit architecture variant) machine")
  (cpu scarts_16bf)
  (bfd-name "scarts_16")
  (isas scarts_16)
)

; CPU variant (machine) model definitions
(define-model
  (name scarts_16gm)
  (comment "SCARTS (16-bit architecture variant) generic model")
  (mach scarts_16)
  (unit u-exec "Execution Unit" () 1 1 () () () ())
)

;----------------------
; Hardware Definitions
;----------------------

; General-purpose registers
(define-keyword
  (name gpr-names)
  (print-name h-gpr)
  (prefix "")
  (values (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
          (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15)
          (rts 14) (rte 15))
)

(dnh h-gpr "general-purpose registers"
  (CACHE-ADDR)
  (register HI (16))
  (extern-keyword gpr-names)
  () ()
)

(include "scarts.cpu")

;--------------------------
; Instruction Enumerations
;--------------------------

(define-normal-insn-enum insn-opc-4 "4-bit opcode enum" () OPC4_ f-opc-4
  ((LDLI #x0) (LDHI #x1) (LDLIU #x2))
)

(define-normal-insn-enum insn-opc-5 "5-bit opcode enum" () OPC5_ f-opc-5
  ((CMPI_EQ #x17) (CMPI_LT #x6) (CMPI_GT #x7))
)

(define-normal-insn-enum insn-opc-6 "6-bit opcode enum" () OPC6_ f-opc-6
  ((LDFPW #x18) (LDFPX #x19) (LDFPY #x1A) (LDFPZ #x1B)
   (STFPW #x1C) (STFPX #x1D) (STFPY #x1E) (STFPZ #x1F)
   (ADDI #x2A) (ADDI_CT #x26) (ADDI_CF #x22)
   (JMPI #x2B) (JMPI_CT #x27) (JMPI_CF #x23))
)

(define-normal-insn-enum insn-opc-7 "7-bit opcode enum" () OPC7_ f-opc-7
  ((LDFPW_INC #x20) (LDFPX_INC #x22) (LDFPY_INC #x24) (LDFPZ_INC #x26)
   (STFPW_INC #x28) (STFPX_INC #x2A) (STFPY_INC #x2C) (STFPZ_INC #x2E)
   (LDFPW_DEC #x21) (LDFPX_DEC #x23) (LDFPY_DEC #x25) (LDFPZ_DEC #x27)
   (STFPW_DEC #x29) (STFPX_DEC #x2B) (STFPY_DEC #x2D) (STFPZ_DEC #x2F)
   (LDVEC #x7D) (STVEC #x7E))
)

(define-normal-insn-enum insn-opc-8 "8-bit opcode enum" () OPC8_ f-opc-8
  ((CMP_EQ #xB0) (CMP_LT #xB1) (CMP_GT #xB2)
   (CMPU_LT #xB3) (CMPU_GT #xB4)
   (BTEST #xB6)
   (BSET #xA4) (BSET_CT #x94) (BSET_CF #x84)
   (BCLR #xA6) (BCLR_CT #x96) (BCLR_CF #x86)
   (SL #xA0) (SL_CT #x90) (SL_CF #x80)
   (SLI #xA1) (SLI_CT #x91) (SLI_CF #x81)
   (SR #xA2) (SR_CT #x92) (SR_CF #x82)
   (SRI #xA3) (SRI_CT #x93) (SRI_CF #x83)
   (SRA #xE8) (SRA_CT #xD8) (SRA_CF #xC8)
   (SRAI #xE9) (SRAI_CT #xD9) (SRAI_CF #xC9)
   (MOV #xE0) (MOV_CT #xD0) (MOV_CF #xC0)
   (ADD #xE1) (ADD_CT #xD1) (ADD_CF #xC1)
   (ADDC #xE2) (ADDC_CT #xD2) (ADDC_CF #xC2)
   (SUB #xE3) (SUB_CT #xD3) (SUB_CF #xC3)
   (SUBC #xE4) (SUBC_CT #xD4) (SUBC_CF #xC4)
   (AND #xE5) (AND_CT #xD5) (AND_CF #xC5)
   (OR #xE6) (OR_CT #xD6) (OR_CF #xC6)
   (EOR #xE7) (EOR_CT #xD7) (EOR_CF #xC7)
   (LDH #xF1) (LDB #xF3) (LDBU #xF4)
   (STH #xF6) (STB #xF7)
   (TRAP #xEB) (TRAP_CT #xDB) (TRAP_CF #xCB))
)

(define-normal-insn-enum insn-opc-12 "12-bit opcode enum" () OPC12_ f-opc-12
  ((RRC #xEA0) (RRC_CT #xDA0) (RRC_CF #xCA0)
   (NOT #xEC0) (NOT_CT #xDC0) (NOT_CF #xCC0)
   (NEG #xED0) (NEG_CT #xDD0) (NEG_CF #xCD0)
   (JSR #xEE0) (JSR_CT #xDE0) (JSR_CF #xCE0)
   (JMP #xEF0) (JMP_CT #xDF0) (JMP_CF #xCF0))
)

(define-normal-insn-enum insn-opc-16 "16-bit opcode enum" () OPC16_ f-opc-16
  ((RTS #xF80E) (RTE #xF90F)
   (NOP #xFE00) (ILLOP #xFFFF))
)

;---------------------------------
; Arithmetic Logical Instructions
;---------------------------------

(m-opc5-reg-simm7-insn   cmpi_eq   CMPI_EQ   "Compare equal immediate"          ())
(m-opc5-reg-simm7-insn   cmpi_lt   CMPI_LT   "Compare less than immediate"      ())
(m-opc5-reg-simm7-insn   cmpi_gt   CMPI_GT   "Compare greater than immediate"   ())

(m-opc6-reg-simm6-insn   addi      ADDI      "Add immediate"                      ())
(m-opc6-reg-simm6-insn   addi_ct   ADDI_CT   "Add immediate if cond-flag true"    ())
(m-opc6-reg-simm6-insn   addi_cf   ADDI_CF   "Add immediate if cond-flag false"   ())

(m-opc8-reg-uimm4-insn   sli       SLI       "Shift left immediate"                                  ())
(m-opc8-reg-uimm4-insn   sli_ct    SLI_CT    "Shift left immediate if cond-flag true"                ())
(m-opc8-reg-uimm4-insn   sli_cf    SLI_CF    "Shift left immediate if cond-flag false"               ())
(m-opc8-reg-uimm4-insn   sri       SRI       "Shift right immediate"                                 ())
(m-opc8-reg-uimm4-insn   sri_ct    SRI_CT    "Shift right immediate if cond-flag true"               ())
(m-opc8-reg-uimm4-insn   sri_cf    SRI_CF    "Shift right immediate if cond-flag false"              ())
(m-opc8-reg-uimm4-insn   srai      SRAI      "Shift right arithmetic immediate"                      ())
(m-opc8-reg-uimm4-insn   srai_ct   SRAI_CT   "Shift right arithmetic immediate if cond-flag true"    ())
(m-opc8-reg-uimm4-insn   srai_cf   SRAI_CF   "Shift right arithmetic immediate if cond-flag false"   ())

(m-opc8-reg-reg-insn   cmp_eq    CMP_EQ     "Compare equal"                                     ())
(m-opc8-reg-reg-insn   cmp_lt    CMP_LT     "Compare less than"                                 ())
(m-opc8-reg-reg-insn   cmp_gt    CMP_GT     "Compare greater than"                              ())
(m-opc8-reg-reg-insn   cmpu_lt   CMPU_LT    "Compare less than unsigned"                        ())
(m-opc8-reg-reg-insn   cmpu_gt   CMPU_GT    "Compare greater than unsigned"                     ())
(m-opc8-reg-reg-insn   sl        SL         "Shift left"                                        ())
(m-opc8-reg-reg-insn   sl_ct     SL_CT      "Shift left if cond-flag true"                      ())
(m-opc8-reg-reg-insn   sl_cf     SL_CF      "Shift left if cond-flag false"                     ())
(m-opc8-reg-reg-insn   sr        SR         "Shift right"                                       ())
(m-opc8-reg-reg-insn   sr_ct     SR_CT      "Shift right if cond-flag true"                     ())
(m-opc8-reg-reg-insn   sr_cf     SR_CF      "Shift right if cond-flag false"                    ())
(m-opc8-reg-reg-insn   sra       SRA        "Shift right arithmetic"                            ())
(m-opc8-reg-reg-insn   sra_ct    SRA_CT     "Shift right arithmetic if cond-flag true"          ())
(m-opc8-reg-reg-insn   sra_cf    SRA_CF     "Shift right arithmetic if cond-flag false"         ())
(m-opc8-reg-reg-insn   add       ADD        "Add"                                               ())
(m-opc8-reg-reg-insn   add_ct    ADD_CT     "Add if cond-flag true"                             ())
(m-opc8-reg-reg-insn   add_cf    ADD_CF     "Add if cond-flag false"                            ())
(m-opc8-reg-reg-insn   addc      ADDC       "Add with carry"                                    ())
(m-opc8-reg-reg-insn   addc_ct   ADDC_CT    "Add with carry if cond-flag true"                  ())
(m-opc8-reg-reg-insn   addc_cf   ADDC_CF    "Add with carry if cond-flag false"                 ())
(m-opc8-reg-reg-insn   sub       SUB        "Subtract"                                          ())
(m-opc8-reg-reg-insn   sub_ct    SUB_CT     "Subtract if cond-flag true"                        ())
(m-opc8-reg-reg-insn   sub_cf    SUB_CF     "Subtract if cond-flag false"                       ())
(m-opc8-reg-reg-insn   subc      SUBC       "Subtract with carry"                               ())
(m-opc8-reg-reg-insn   subc_ct   SUBC_CT    "Subtract with carry if cond-flag true"             ())
(m-opc8-reg-reg-insn   subc_cf   SUBC_CF    "Subtract with carry if cond-flag false"            ())
(m-opc8-reg-reg-insn   and       AND        "Bitwise logical and"                               ())
(m-opc8-reg-reg-insn   and_ct    AND_CT     "Bitwise logical and if cond-flag true"             ())
(m-opc8-reg-reg-insn   and_cf    AND_CF     "Bitwise logical and if cond-flag false"            ())
(m-opc8-reg-reg-insn   or        OR         "Bitwise logical or"                                ())
(m-opc8-reg-reg-insn   or_ct     OR_CT      "Bitwise logical or if cond-flag true"              ())
(m-opc8-reg-reg-insn   or_cf     OR_CF      "Bitwise logical or if cond-flag false"             ())
(m-opc8-reg-reg-insn   eor       EOR        "Bitwise logical exclusive or"                      ())
(m-opc8-reg-reg-insn   eor_ct    EOR_CT     "Bitwise logical exclusive or if cond-flag true"    ())
(m-opc8-reg-reg-insn   eor_cf    EOR_CF     "Bitwise logical exclusive or if cond-flag false"   ())

(m-opc12-reg-insn   rrc      RRC      "Rotate right with carry"                      ())
(m-opc12-reg-insn   rrc_ct   RRC_CT   "Rotate right with carry if cond-flag true"    ())
(m-opc12-reg-insn   rrc_cf   RRC_CF   "Rotate right with carry if cond-flag false"   ())
(m-opc12-reg-insn   not      NOT      "Bitwise logical not"                          ())
(m-opc12-reg-insn   not_ct   NOT_CT   "Bitwise logical not if cond-flag true"        ())
(m-opc12-reg-insn   not_cf   NOT_CF   "Bitwise logical not if cond-flag false"       ())
(m-opc12-reg-insn   neg      NEG      "Negative"                                     ())
(m-opc12-reg-insn   neg_ct   NEG_CT   "Negative if cond-flag true"                   ())
(m-opc12-reg-insn   neg_cf   NEG_CF   "Negative if cond-flag false"                  ())

;-------------------------------
; Control Transfer Instructions
;-------------------------------

(m-opc6-saddr10-pcrel-insn   jmpi      JMPI      "Jump immediate"                      (UNCOND-CTI))
(m-opc6-saddr10-pcrel-insn   jmpi_ct   JMPI_CT   "Jump immediate if cond-flag true"    (COND-CTI))
(m-opc6-saddr10-pcrel-insn   jmpi_cf   JMPI_CF   "Jump immediate if cond-flag false"   (COND-CTI))

(m-opc12-reg-insn   jsr      JSR      "Jump to subroutine"                      (UNCOND-CTI))
(m-opc12-reg-insn   jsr_ct   JSR_CT   "Jump to subroutine if cond-flag true"    (COND-CTI))
(m-opc12-reg-insn   jsr_cf   JSR_CF   "Jump to subroutine if cond-flag false"   (COND-CTI))
(m-opc12-reg-insn   jmp      JMP      "Jump"                                    (UNCOND-CTI))
(m-opc12-reg-insn   jmp_ct   JMP_CT   "Jump if cond-flag true"                  (COND-CTI))
(m-opc12-reg-insn   jmp_cf   JMP_CF   "Jump if cond-flag false"                 (COND-CTI))

;-----------------------------
; Load and Store Instructions
;-----------------------------

(m-opc4-reg-simm8-insn   ldli    LDLI    "Load low byte immediate"                          ())
(m-opc4-reg-simm8-insn   ldhi    LDHI    "Load high byte immediate"                         ())
(m-opc4-reg-uimm8-insn   ldliu   LDLIU   "Load low byte immediate without sign extension"   ())

(m-opc6-reg-simm6-insn   ldfpw   LDFPW   "Load (half)word with frame pointer W"    ())
(m-opc6-reg-simm6-insn   ldfpx   LDFPX   "Load (half)word with frame pointer X"    ())
(m-opc6-reg-simm6-insn   ldfpy   LDFPY   "Load (half)word with frame pointer Y"    ())
(m-opc6-reg-simm6-insn   ldfpz   LDFPZ   "Load (half)word with frame pointer Z"    ())
(m-opc6-reg-simm6-insn   stfpw   STFPW   "Store (half)word with frame pointer W"   ())
(m-opc6-reg-simm6-insn   stfpx   STFPX   "Store (half)word with frame pointer X"   ())
(m-opc6-reg-simm6-insn   stfpy   STFPY   "Store (half)word with frame pointer Y"   ())
(m-opc6-reg-simm6-insn   stfpz   STFPZ   "Store (half)word with frame pointer Z"   ())

(m-opc7-reg-simm5-insn   ldfpw_inc   LDFPW_INC   "Load (half)word with frame pointer W and increment W"    ())
(m-opc7-reg-simm5-insn   ldfpx_inc   LDFPX_INC   "Load (half)word with frame pointer X and increment X"    ())
(m-opc7-reg-simm5-insn   ldfpy_inc   LDFPY_INC   "Load (half)word with frame pointer Y and increment Y"    ())
(m-opc7-reg-simm5-insn   ldfpz_inc   LDFPZ_INC   "Load (half)word with frame pointer Z and increment Z"    ())
(m-opc7-reg-simm5-insn   ldfpw_dec   LDFPW_DEC   "Load (half)word with frame pointer W and decrement W"    ())
(m-opc7-reg-simm5-insn   ldfpx_dec   LDFPX_DEC   "Load (half)word with frame pointer X and decrement X"    ())
(m-opc7-reg-simm5-insn   ldfpy_dec   LDFPY_DEC   "Load (half)word with frame pointer Y and decrement Y"    ())
(m-opc7-reg-simm5-insn   ldfpz_dec   LDFPZ_DEC   "Load (half)word with frame pointer Z and decrement Z"    ())
(m-opc7-reg-simm5-insn   stfpw_inc   STFPW_INC   "Store (half)word with frame pointer W and increment W"   ())
(m-opc7-reg-simm5-insn   stfpx_inc   STFPX_INC   "Store (half)word with frame pointer X and increment X"   ())
(m-opc7-reg-simm5-insn   stfpy_inc   STFPY_INC   "Store (half)word with frame pointer Y and increment Y"   ())
(m-opc7-reg-simm5-insn   stfpz_inc   STFPZ_INC   "Store (half)word with frame pointer Z and increment Z"   ())
(m-opc7-reg-simm5-insn   stfpw_dec   STFPW_DEC   "Store (half)word with frame pointer W and decrement W"   ())
(m-opc7-reg-simm5-insn   stfpx_dec   STFPX_DEC   "Store (half)word with frame pointer X and decrement X"   ())
(m-opc7-reg-simm5-insn   stfpy_dec   STFPY_DEC   "Store (half)word with frame pointer Y and decrement Y"   ())
(m-opc7-reg-simm5-insn   stfpz_dec   STFPZ_DEC   "Store (half)word with frame pointer Z and decrement Z"   ())

(m-opc8-reg-reg-insn   ldh    LDH    "Load halfword"            ())
(m-opc8-reg-reg-insn   ldb    LDB    "Load byte"                ())
(m-opc8-reg-reg-insn   ldbu   LDBU   "Load byte unsigned"       ())
(m-opc8-reg-reg-insn   sth    STH    "Store halfword"           ())
(m-opc8-reg-reg-insn   stb    STB    "Store byte"               ())

;-------------------
; Misc Instructions
;-------------------

(m-opc7-reg-simm5-insn   ldvec      LDVEC      "Load vector"                    ())
(m-opc7-reg-simm5-insn   stvec      STVEC      "Store vector"                   ())

(m-opc8-reg-uimm4-insn   btest      BTEST      "Bit test"                       ())
(m-opc8-reg-uimm4-insn   bset       BSET       "Bit set"                        ())
(m-opc8-reg-uimm4-insn   bset_ct    BSET_CT    "Bit set if cond-flag true"      ())
(m-opc8-reg-uimm4-insn   bset_cf    BSET_CF    "Bit set if cond-flag false"     ())
(m-opc8-reg-uimm4-insn   bclr       BCLR       "Bit clear"                      ())
(m-opc8-reg-uimm4-insn   bclr_ct    BCLR_CT    "Bit clear if cond-flag true"    ())
(m-opc8-reg-uimm4-insn   bclr_cf    BCLR_CF    "Bit clear if cond-flag false"   ())
(m-opc8-reg-uimm4-insn   trap       TRAP       "Trap"                           ())
(m-opc8-reg-uimm4-insn   trap_ct    TRAP_CT    "Trap if cond-flag true"         ())
(m-opc8-reg-uimm4-insn   trap_cf    TRAP_CF    "Trap if cond-flag false"        ())

(m-opc8-reg-reg-insn   mov      MOV      "Move"                      ())
(m-opc8-reg-reg-insn   mov_ct   MOV_CT   "Move if cond-flag true"    ())
(m-opc8-reg-reg-insn   mov_cf   MOV_CF   "Move if cond-flag false"   ())

(m-opc16-insn   rts     RTS     "Return from subroutine"   ())
(m-opc16-insn   rte     RTE     "Return from exception"    ())
(m-opc16-insn   nop     NOP     "No operation"             ())
(m-opc16-insn   illop   ILLOP   "Illegal operation"        ())