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%%%% WISHBONE SD Card Controller IP Core                          %%%%
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%%%% sw_if.tex                                                    %%%%
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%%%% This file is part of the WISHBONE SD Card                    %%%%
%%%% Controller IP Core project                                   %%%%
%%%% http://www.opencores.org/cores/xxx/                          %%%%
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%%%% Description                                                  %%%%
%%%% documentation 'Software interface' chapter                   %%%%
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%%%% Author(s):                                                   %%%%
%%%%     - Marek Czerski, ma.czerski@gmail.com                    %%%%
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%%%% Copyright (C) 2013 Authors                                   %%%%
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%%%% the original copyright notice and the associated disclaimer. %%%%
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%%%% This source file is free software; you can redistribute it   %%%%
%%%% and/or modify it under the terms of the GNU Lesser General   %%%%
%%%% Public License as published by the Free Software Foundation; %%%%
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%%%% later version.                                               %%%%
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%%%% This source is distributed in the hope that it will be       %%%%
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\section{Software interface}
\label{sec:sw_if}
 
    Access to IP core registers is provided through Wishbone slave interface. 
 
    \subsection{IP Core registers}
    \label{sec:regs}
 
    \begin{table}[H]
    \caption{List of registers}
        \begin{tabular}{l|l|l|l}
                \rowcolor[gray]{0.7} name & address & access & description \\ \hline \hline
                \texttt{argument} & \texttt{0x00} & RW & command argument \\ \hline
                \texttt{command} & \texttt{0x04} & RW & command transaction configuration \\ \hline
                \texttt{response0} & \texttt{0x08} & R & bits 31-0 of the response \\ \hline
                \texttt{response1} & \texttt{0x0C} & R & bits 63-32 of the response \\ \hline
                \texttt{response2} & \texttt{0x10} & R & bits 95-64 of the response \\ \hline
                \texttt{response3} & \texttt{0x14} & R & bits 119-96 of the response \\ \hline
                \texttt{control} & \texttt{0x1C} & RW & IP core control settings \\ \hline
                \texttt{timeout} & \texttt{0x20} & RW & timeout configuration \\ \hline
                \texttt{clock\_devider} & \texttt{0x24} & RW & MMC/SD interface clock devider \\ \hline
                \texttt{reset} & \texttt{0x28} & RW & software reset \\ \hline
                \texttt{voltage} & \texttt{0x2C} & R & power control information \\ \hline
                \texttt{capabilities} & \texttt{0x30} & R & capabilities information \\ \hline
                \texttt{cmd\_event\_status} & \texttt{0x34} & RW & command transaction events status / clear \\ \hline
                \texttt{cmd\_event\_enable} & \texttt{0x38} & RW & command transaction events enable \\ \hline
                \texttt{data\_event\_status} & \texttt{0x3C} & RW & data transaction events status / clear \\ \hline
                \texttt{data\_event\_enable} & \texttt{0x38} & RW & data transaction events enable \\ \hline
                \texttt{blkock\_size} & \texttt{0x44} & RW & read / write block transfer size \\ \hline
                \texttt{blkock\_count} & \texttt{0x48} & RW & read / write block count \\ \hline
                \texttt{dst\_src\_address} & \texttt{0x60} & RW & DMA destination / source address \\ \hline
                \hline
        \end{tabular}
        \label{tab:registers}
    \end{table}
 
    \subsubsection{Argument register}
    \label{sec:arg_reg}
 
    Write operation to this register triggers command transaction (command register has to be configured before writing to this register).
 
    \begin{table}[H]
    \caption{Argument register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:0]} & \texttt{0x00000000} & RW & command argument value. \\ \hline
                \hline
        \end{tabular}
        \label{tab:arg_reg}
    \end{table}
 
    \subsubsection{Command register}
    \label{sec:cmd_reg}
 
    This register configures all aspects of command to be sent.
 
    \begin{table}[H]
    \caption{Command register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:14]} & &  & reserved \\ \hline
                \texttt{[13:8]} & \texttt{0x00} & RW & command index \\ \hline
                \texttt{[7]} & & & reserved \\ \hline
                \texttt{[6:5]} & \texttt{0x0} & RW & data transfer specification. 0x0 - no data transfer; 0x1 - triggers read data transaction after command transaction;
                0x2 - triggers write data transaction after command transaction\\ \hline
                \texttt{[4]} & \texttt{0x0} & RW & check response for correct command index \\ \hline
                \texttt{[3]} & \texttt{0x0} & RW & check response crc \\ \hline
                \texttt{[2]} & \texttt{0x0} & RW & check for busy signal after command transaction (if busy signal will be asserted after command transaction, 
                core will wait for as long as busy signal remains) \\ \hline
                \texttt{[1:0]} & \texttt{0x0} & RW & response check configuration. 0x0 - don't wait for response; 0x1 - wait for short response (48-bits);
                0x2 - wait for long response (136-bits) \\ \hline
                \hline
        \end{tabular}
        \label{tab:cmd_reg}
    \end{table}
 
    \subsubsection{Response register 0-3}
    \label{sec:resp_reg}
 
    Response registers 0-3 contains response data bits after end of succesful command transaction (if bits 1-0 of command register were configured to wait for response).
 
    \begin{table}[H]
    \caption{Response register 0-3}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:0]} & \texttt{0x00000000} & R & response data bits \\ \hline
                \hline
        \end{tabular}
        \label{tab:resp_reg}
    \end{table}
 
 
    \subsubsection{Control register}
    \label{sec:control_reg}
 
    \begin{table}[H]
    \caption{Control register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:1]} & & & reserved \\ \hline
                \texttt{[0]} & \texttt{0x0} & RW & MMC/SD bus width; 0x0 - 1-bit operation; 0x1 - 4-bit operation \\ \hline
                \hline
        \end{tabular}
        \label{tab:control_reg}
    \end{table}
 
    \subsubsection{Timeout register}
    \label{sec:timeout_reg}
 
    Timeout register configures transaction watchdog counter. If any transaction will last longer than configured timeout, interrupt will be generated.
    Value in timeout register represents the number of \texttt{sd\_clk\_o\_pad} clock cyckles. Register value is calculated by following formula:
    \begin{equation}
    REG = \frac{timeout[s] * frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]}{(2*(\texttt{clock\_devider} + 1))}
    \end{equation} 
 
    \begin{table}[H]
    \caption{Timeout register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:16]} & & & reserved \\ \hline
                \texttt{[15:0]} & \texttt{0x0} & RW & timeout value \\ \hline
                \hline
        \end{tabular}
        \label{tab:timeout_reg}
    \end{table}
 
    \subsubsection{Clock devider register}
    \label{sec:div_reg}
 
    Clock devider register control division of \texttt{sd\_clk\_i\_pad} signal frequency. Output of this devider is routed to MMC/SD interface clock domain.
    Register value is calculated by following formula:
    \begin{equation}
    REG = \frac{frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]}{2*frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]} - 1
    \end{equation} 
 
    \begin{table}[H]
    \caption{Clock devider register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:8]} & & & reserved \\ \hline
                \texttt{[7:0]} & \texttt{0x0} & RW & devider ratio \\ \hline
                \hline
        \end{tabular}
        \label{tab:div_reg}
    \end{table}
 
    \subsubsection{Software reset register}
    \label{sec:reset_reg}
 
    \begin{table}[H]
    \caption{Software reset register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:1]} & & & reserved \\ \hline
                \texttt{[0]} & \texttt{0x0} & RW & reset; 0x0 - no reset; 0x1 - reset applied \\ \hline
                \hline
        \end{tabular}
        \label{tab:reset_reg}
    \end{table}
 
    \subsubsection{Voltage information register}
    \label{sec:voltage_reg}
 
    This register contains the value of power supply voltage expressed in mV. It is read-only register and its
    value is configured in HDL.
 
    \begin{table}[H]
    \caption{Software reset register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:0]} & & R & power supply voltage [mV] \\ \hline
                \hline
        \end{tabular}
        \label{tab:voltage_reg}
    \end{table}
 
    \subsubsection{Capabilities information register}
    \label{sec:capa_reg}
 
    \begin{table}[H]
    \caption{Capabilities information register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:0]} & & & reserved \\ \hline
                \hline
        \end{tabular}
        \label{tab:capa_reg}
    \end{table}
 
    \subsubsection{Command events status register}
    \label{sec:cmd_evt_reg}
 
    This register holds all pending event flags related to command transactions. Write operation to this register
    clears all flags.
 
    \begin{table}[H]
    \caption{Command events status register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:5]} & & & reserved \\ \hline
                \texttt{[4]} & \texttt{0x0} & RW & index error event \\ \hline
                \texttt{[3]} & \texttt{0x0} & RW & crc error event \\ \hline
                \texttt{[2]} & \texttt{0x0} & RW & timeout error event \\ \hline
                \texttt{[1]} & \texttt{0x0} & RW & error event (logic sum of all error events) \\ \hline
                \texttt{[0]} & \texttt{0x0} & RW & command transaction succesful completion event \\ \hline
                \hline
        \end{tabular}
        \label{tab:cmd_evt_reg}
    \end{table}
 
    \subsubsection{Command transaction events enable register}
    \label{sec:cmd_ena_reg}
 
    This register acts as event \textit{and} mask. To enable given event, corresponding bit must be set to 1.
 
    \begin{table}[H]
    \caption{Command transaction events enable register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:5]} & & & reserved \\ \hline
                \texttt{[4]} & \texttt{0x0} & RW & enable index error event \\ \hline
                \texttt{[3]} & \texttt{0x0} & RW & enable crc error event \\ \hline
                \texttt{[2]} & \texttt{0x0} & RW & enable timeout error event \\ \hline
                \texttt{[1]} & \texttt{0x0} & RW & enable error event (logic sum of all error events) \\ \hline
                \texttt{[0]} & \texttt{0x0} & RW & enable command transaction succesful completion event \\ \hline
                \hline
        \end{tabular}
        \label{tab:cmd_ena_reg}
    \end{table}
 
    \subsubsection{Data transaction events status register}
    \label{sec:data_evt_reg}
 
    This register holds all pending event flags related to data transactions. Write operation to this register
    clears all flags.
 
    \begin{table}[H]
    \caption{Data transaction events status register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:3]} & & & reserved \\ \hline
                \texttt{[2]} & \texttt{0x0} & RW & fifo error event \\ \hline
                \texttt{[1]} & \texttt{0x0} & RW & crc error event \\ \hline
                \texttt{[0]} & \texttt{0x0} & RW & data transaction succesful completion event \\ \hline
                \hline
        \end{tabular}
        \label{tab:data_evt_reg}
    \end{table}
 
    \subsubsection{Data transaction events enable register}
    \label{sec:data_ena_reg}
 
    This register acts as event \textit{and} mask. To enable given event, corresponding bit must be set to 1.
 
    \begin{table}[H]
    \caption{Data transaction events enable register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:3]} & & & reserved \\ \hline
                \texttt{[2]} & \texttt{0x0} & RW & enable fifo error event \\ \hline
                \texttt{[1]} & \texttt{0x0} & RW & enable crc error event \\ \hline
                \texttt{[0]} & \texttt{0x0} & RW & enable data transaction succesful completion event \\ \hline
                \hline
        \end{tabular}
        \label{tab:data_ena_reg}
    \end{table}
 
    \subsubsection{Block size register}
    \label{sec:blocksize_reg}
 
    This register controls the number of bytes to write/read in a single block. Data transaction will transmit number of bytes equal to value of this register times value
    of \texttt{blkock\_count} register.
 
    \begin{table}[H]
    \caption{Block size register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:12]} & & & reserved \\ \hline
                \texttt{[11:0]} & \texttt{0x200} & RW & number of byes in a single block \\ \hline
                \hline
        \end{tabular}
        \label{tab:blocksize_reg}
    \end{table}
 
    \subsubsection{Block count register}
    \label{sec:blockcnt_reg}
 
    This register controls the number of blocks to write/read in data transaction. Data transaction will transmit number of bytes equal to value of this register times value
    of \texttt{blkock\_size} register.
 
    \begin{table}[H]
    \caption{Block count register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:12]} & & & reserved \\ \hline
                \texttt{[11:0]} & \texttt{0x200} & RW & number of blocks in data transaction \\ \hline
                \hline
        \end{tabular}
        \label{tab:blockcnt_reg}
    \end{table}
 
    \subsubsection{DMA destination / source register}
    \label{sec:dst_src_reg}
 
    This registers configures the DMA source / destination address. For write transactions, this address points to the begining of data block to be sent.
    For read transactions, this address points to the begining of data block to be written.
 
    \begin{table}[H]
    \caption{DMA destination / source register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:o]} & 0x00000000 & RW & address \\ \hline
                \hline
        \end{tabular}
        \label{tab:dst_src_reg}
    \end{table}