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https://opencores.org/ocsvn/sd_card_controller/sd_card_controller/trunk
Subversion Repositories sd_card_controller
[/] [sd_card_controller/] [trunk/] [syn/] [quartus/] [bin/] [Makefile] - Rev 9
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######################################################################
#### ####
#### WISHBONE SD Card Controller IP Core ####
#### ####
#### Makefile ####
#### ####
#### This file is part of the WISHBONE SD Card ####
#### Controller IP Core project ####
#### http://opencores.org/project,sd_card_controller ####
#### ####
#### Description ####
#### Altera synthesis makefile ####
#### ####
#### Author(s): ####
#### - Marek Czerski, ma.czerski@gmail.com ####
#### ####
######################################################################
#### ####
#### Copyright (C) 2013 Authors ####
#### ####
#### Based on original work by ####
#### Stefan Kristiansson, stefan.kristiansson@saunalahti.fi ####
#### ####
#### Copyright (C) 2009,2010,2011 Authors and OPENCORES.ORG ####
#### ####
#### This source file may be used and distributed without ####
#### restriction provided that this copyright statement is not ####
#### removed from the file and that any derivative work contains ####
#### the original copyright notice and the associated disclaimer. ####
#### ####
#### This source file is free software; you can redistribute it ####
#### and/or modify it under the terms of the GNU Lesser General ####
#### Public License as published by the Free Software Foundation; ####
#### either version 2.1 of the License, or (at your option) any ####
#### later version. ####
#### ####
#### This source is distributed in the hope that it will be ####
#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
#### PURPOSE. See the GNU Lesser General Public License for more ####
#### details. ####
#### ####
#### You should have received a copy of the GNU Lesser General ####
#### Public License along with this source; if not, download it ####
#### from http://www.opencores.org/lgpl.shtml ####
#### ####
######################################################################
V ?= @
QUARTUS_DIR ?= /opt/altera/11.0/quartus
QUARTUS = $(QUARTUS_DIR)/bin/quartus
SH = $(QUARTUS_DIR)/bin/quartus_sh
PGM = $(QUARTUS_DIR)/bin/quartus_pgm
STA = $(QUARTUS_DIR)/bin/quartus_sta
ASM = $(QUARTUS_DIR)/bin/quartus_asm
FIT = $(QUARTUS_DIR)/bin/quartus_fit
MAP = $(QUARTUS_DIR)/bin/quartus_map
RUN_DIR=$(shell pwd)
BIN_DIR=$(RUN_DIR)/../bin
RTL_TOP ?= sdc_controller_top
DESIGN_NAME ?= sdc_controller
FPGA_FAMILY ?= "Cyclone IV E"
FPGA_PART ?= EP4CE40F29C8
RTL_VERILOG_SRC = $(shell ls ../../../rtl/verilog/*.v ../src/*.v)
RTL_VERILOG_INCLUDE_DIR = ../../../rtl/verilog
TCL_FILE=$(DESIGN_NAME).tcl
SDC_FILE=$(DESIGN_NAME).sdc
QPF_FILE=$(DESIGN_NAME).qpf
all: sta
$(TCL_FILE): $(BIN_DIR)/pin_assignments.tcl $(RTL_VERILOG_SRC) $(BOARD_BACKEND_VERILOG_SRC) $(RTL_VHDL_SRC)
$(V)echo; echo "#### Generating TCL file ####"; echo
$(V)echo "# TCL Script for SD Controller Synthesis" > $@
$(V)echo "# This file is autogenerated - any changes will be overwritten" >> $@
$(V)echo "# See the Makefile in syn/quartus/bin to make changes" >> $@
$(V)echo "project_new $(DESIGN_NAME) -overwrite" >> $@
$(V)echo "set_global_assignment -name FAMILY \"$(FPGA_FAMILY)\"" >> $@
$(V)echo "set_global_assignment -name DEVICE $(FPGA_PART)" >> $@
$(V)echo "set_global_assignment -name TOP_LEVEL_ENTITY $(RTL_TOP)" >> $@
$(V)for file in $(RTL_VERILOG_SRC); do \
echo "set_global_assignment -name VERILOG_FILE $$file" >> $@ ; \
done
$(V)for file in $(BOARD_BACKEND_VERILOG_SRC); do \
echo "set_global_assignment -name VERILOG_FILE $$file" >> $@ ; \
done
$(V)for file in $(RTL_VHDL_SRC); do \
echo "set_global_assignment -name VHDL_FILE $$file" >> $@ ; \
done
$(V)echo "set_global_assignment -name SEARCH_PATH $(RTL_VERILOG_INCLUDE_DIR)" >> $@
$(V)echo "set_global_assignment -name SDC_FILE $(DESIGN_NAME).sdc" >> $@
# Do pin assignments
$(V)if [ -f $(BIN_DIR)/pin_assignments.tcl ]; then \
cat $(BIN_DIR)/pin_assignments.tcl >> $@ ; \
fi;
$(V)echo "project_close" >> $@
$(V)echo
$(SDC_FILE): $(BIN_DIR)/constraints.sdc
$(V)echo; echo "#### Generating SDC file ####"; echo
$(V)echo "# SDC file for SD Controller" > $@
$(V)echo "# This file is autogenerated - any changes will be overwritten" >> $@
$(V)echo "# See the Makefile in syn/quartus/bin to make changes" >> $@
$(V)if [ -f $(BIN_DIR)/constraints.sdc ]; then \
cat $(BIN_DIR)/constraints.sdc >> $@ ; \
fi;
$(V)echo
$(QPF_FILE): $(TCL_FILE) $(SDC_FILE)
$(V) echo "#### Generating project files ####"
$(V)$(SH) -t $(TCL_FILE)
project: $(QPF_FILE)
quartus: $(QPF_FILE)
$(V)$(QUARTUS) $(QPF_FILE)
pgm:
$(V)$(PGM) --mode=jtag -o p\;$(DESIGN_NAME).sof
sta: asm
$(V)$(STA) $(DESIGN_NAME)
asm: fit
$(V)$(ASM) $(DESIGN_NAME)
fit: map
$(V)$(FIT) $(DESIGN_NAME)
map: project
$(V)$(MAP) $(DESIGN_NAME)
print_config:
$(V)echo; echo "### Synthesis make configuration ###"; echo
$(V)echo "FPGA_FAMILY="$(FPGA_FAMILY)
$(V)echo "FPGA_PART="$(FPGA_PART)
$(V)echo
print_rtl_sources:
$(V)echo $(RTL_VERILOG_SRC)
clean:
rm -rf *.* db incremental_db
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