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[/] [sdcard_mass_storage_controller/] [trunk/] [backend/] [Actel/] [Block/] [versatile_fifo_dptam_dw/] [datasheet_report.log] - Rev 15

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SmartTime Version 3.0
Actel Corporation - Actel Designer Software Release v8.5 (Version 8.5.0.34)

 Design                         versatile_fifo_dptam_dw  
 Family                         ProASIC3                 
 Die                            A3P1000                  
 Package                        208 PQFP                 
 Temperature                    COM                      
 Voltage                        COM                      
 Speed Grade                    STD                      
 Design State                   Post-Layout              
 Data source                    Silicon verified         
 Analysis Min Case              BEST                     
 Analysis Max Case              WORST                    
 Scenario for Timing Analysis   Primary                  

 Using Enhanced Min Delay Analysis
Pin Description
+-----------+----------+--------+----------------+
| Name      | Location | Type   | I/O Technology |
+-----------+----------+--------+----------------+
| d_a[7]    |          | Input  |                |
| d_a[6]    |          | Input  |                |
| d_a[5]    |          | Input  |                |
| d_a[4]    |          | Input  |                |
| d_a[3]    |          | Input  |                |
| d_a[2]    |          | Input  |                |
| d_a[1]    |          | Input  |                |
| d_a[0]    |          | Input  |                |
| q_a[7]    |          | Output |                |
| q_a[6]    |          | Output |                |
| q_a[5]    |          | Output |                |
| q_a[4]    |          | Output |                |
| q_a[3]    |          | Output |                |
| q_a[2]    |          | Output |                |
| q_a[1]    |          | Output |                |
| q_a[0]    |          | Output |                |
| adr_a[10] |          | Input  |                |
| adr_a[9]  |          | Input  |                |
| adr_a[8]  |          | Input  |                |
| adr_a[7]  |          | Input  |                |
| adr_a[6]  |          | Input  |                |
| adr_a[5]  |          | Input  |                |
| adr_a[4]  |          | Input  |                |
| adr_a[3]  |          | Input  |                |
| adr_a[2]  |          | Input  |                |
| adr_a[1]  |          | Input  |                |
| adr_a[0]  |          | Input  |                |
| we_a      |          | Input  |                |
| clk_a     |          | Clock  |                |
| q_b[7]    |          | Output |                |
| q_b[6]    |          | Output |                |
| q_b[5]    |          | Output |                |
| q_b[4]    |          | Output |                |
| q_b[3]    |          | Output |                |
| q_b[2]    |          | Output |                |
| q_b[1]    |          | Output |                |
| q_b[0]    |          | Output |                |
| adr_b[10] |          | Input  |                |
| adr_b[9]  |          | Input  |                |
| adr_b[8]  |          | Input  |                |
| adr_b[7]  |          | Input  |                |
| adr_b[6]  |          | Input  |                |
| adr_b[5]  |          | Input  |                |
| adr_b[4]  |          | Input  |                |
| adr_b[3]  |          | Input  |                |
| adr_b[2]  |          | Input  |                |
| adr_b[1]  |          | Input  |                |
| adr_b[0]  |          | Input  |                |
| d_b[7]    |          | Input  |                |
| d_b[6]    |          | Input  |                |
| d_b[5]    |          | Input  |                |
| d_b[4]    |          | Input  |                |
| d_b[3]    |          | Input  |                |
| d_b[2]    |          | Input  |                |
| d_b[1]    |          | Input  |                |
| d_b[0]    |          | Input  |                |
| we_b      |          | Input  |                |
| clk_b     |          | Clock  |                |
+-----------+----------+--------+----------------+


DC Electrical Characteristics
Not Applicable


AC Electrical Characteristics
+-------------------+--------------+--------+--------------+--------+---------+------+
| Description       |              |        |              | Min    | Max     | Unit |
+-------------------+--------------+--------+--------------+--------+---------+------+
| Clock frequency   | clk_a        |        |              |        | 231.267 | MHz  |
| Clock period      | clk_a        |        |              | 4.324  |         | ns   |
| Clock frequency   | clk_b        |        |              |        | 231.267 | MHz  |
| Clock period      | clk_b        |        |              | 4.324  |         | ns   |
| Setup time        | adr_a[0]     | before | clk_a (rise) | 0.280  |         | ns   |
| Setup time        | adr_a[10]    | before | clk_a (rise) | 0.280  |         | ns   |
| Setup time        | adr_a[1]     | before | clk_a (rise) | 0.280  |         | ns   |
| Setup time        | adr_a[2]     | before | clk_a (rise) | 0.280  |         | ns   |
| Setup time        | adr_a[3]     | before | clk_a (rise) | 0.280  |         | ns   |
| Setup time        | adr_a[4]     | before | clk_a (rise) | 0.280  |         | ns   |
| Setup time        | adr_a[5]     | before | clk_a (rise) | 0.280  |         | ns   |
| Setup time        | adr_a[6]     | before | clk_a (rise) | 0.280  |         | ns   |
| Setup time        | adr_a[7]     | before | clk_a (rise) | 0.280  |         | ns   |
| Setup time        | adr_a[8]     | before | clk_a (rise) | 0.280  |         | ns   |
| Setup time        | adr_a[9]     | before | clk_a (rise) | 0.280  |         | ns   |
| Setup time        | adr_b[0]     | before | clk_b (rise) | 0.282  |         | ns   |
| Setup time        | adr_b[10]    | before | clk_b (rise) | 0.282  |         | ns   |
| Setup time        | adr_b[1]     | before | clk_b (rise) | 0.282  |         | ns   |
| Setup time        | adr_b[2]     | before | clk_b (rise) | 0.282  |         | ns   |
| Setup time        | adr_b[3]     | before | clk_b (rise) | 0.282  |         | ns   |
| Setup time        | adr_b[4]     | before | clk_b (rise) | 0.282  |         | ns   |
| Setup time        | adr_b[5]     | before | clk_b (rise) | 0.282  |         | ns   |
| Setup time        | adr_b[6]     | before | clk_b (rise) | 0.282  |         | ns   |
| Setup time        | adr_b[7]     | before | clk_b (rise) | 0.282  |         | ns   |
| Setup time        | adr_b[8]     | before | clk_b (rise) | 0.282  |         | ns   |
| Setup time        | adr_b[9]     | before | clk_b (rise) | 0.282  |         | ns   |
| Setup time        | d_a[0]       | before | clk_a (rise) | 0.193  |         | ns   |
| Setup time        | d_a[1]       | before | clk_a (rise) | 0.193  |         | ns   |
| Setup time        | d_a[2]       | before | clk_a (rise) | 0.193  |         | ns   |
| Setup time        | d_a[3]       | before | clk_a (rise) | 0.193  |         | ns   |
| Setup time        | d_a[4]       | before | clk_a (rise) | 0.193  |         | ns   |
| Setup time        | d_a[5]       | before | clk_a (rise) | 0.193  |         | ns   |
| Setup time        | d_a[6]       | before | clk_a (rise) | 0.193  |         | ns   |
| Setup time        | d_a[7]       | before | clk_a (rise) | 0.193  |         | ns   |
| Setup time        | d_b[0]       | before | clk_b (rise) | 0.176  |         | ns   |
| Setup time        | d_b[1]       | before | clk_b (rise) | 0.176  |         | ns   |
| Setup time        | d_b[2]       | before | clk_b (rise) | 0.176  |         | ns   |
| Setup time        | d_b[3]       | before | clk_b (rise) | 0.176  |         | ns   |
| Setup time        | d_b[4]       | before | clk_b (rise) | 0.176  |         | ns   |
| Setup time        | d_b[5]       | before | clk_b (rise) | 0.176  |         | ns   |
| Setup time        | d_b[6]       | before | clk_b (rise) | 0.176  |         | ns   |
| Setup time        | d_b[7]       | before | clk_b (rise) | 0.176  |         | ns   |
| Setup time        | we_a         | before | clk_a (rise) | 2.731  |         | ns   |
| Setup time        | we_b         | before | clk_b (rise) | 3.346  |         | ns   |
| Hold time         | adr_a[0]     | after  | clk_a (rise) | 0.000  |         | ns   |
| Hold time         | adr_a[10]    | after  | clk_a (rise) | 0.000  |         | ns   |
| Hold time         | adr_a[1]     | after  | clk_a (rise) | 0.000  |         | ns   |
| Hold time         | adr_a[2]     | after  | clk_a (rise) | 0.000  |         | ns   |
| Hold time         | adr_a[3]     | after  | clk_a (rise) | 0.000  |         | ns   |
| Hold time         | adr_a[4]     | after  | clk_a (rise) | 0.000  |         | ns   |
| Hold time         | adr_a[5]     | after  | clk_a (rise) | 0.000  |         | ns   |
| Hold time         | adr_a[6]     | after  | clk_a (rise) | 0.000  |         | ns   |
| Hold time         | adr_a[7]     | after  | clk_a (rise) | 0.000  |         | ns   |
| Hold time         | adr_a[8]     | after  | clk_a (rise) | 0.000  |         | ns   |
| Hold time         | adr_a[9]     | after  | clk_a (rise) | 0.000  |         | ns   |
| Hold time         | adr_b[0]     | after  | clk_b (rise) | 0.000  |         | ns   |
| Hold time         | adr_b[10]    | after  | clk_b (rise) | 0.000  |         | ns   |
| Hold time         | adr_b[1]     | after  | clk_b (rise) | 0.000  |         | ns   |
| Hold time         | adr_b[2]     | after  | clk_b (rise) | 0.000  |         | ns   |
| Hold time         | adr_b[3]     | after  | clk_b (rise) | 0.000  |         | ns   |
| Hold time         | adr_b[4]     | after  | clk_b (rise) | 0.000  |         | ns   |
| Hold time         | adr_b[5]     | after  | clk_b (rise) | 0.000  |         | ns   |
| Hold time         | adr_b[6]     | after  | clk_b (rise) | 0.000  |         | ns   |
| Hold time         | adr_b[7]     | after  | clk_b (rise) | 0.000  |         | ns   |
| Hold time         | adr_b[8]     | after  | clk_b (rise) | 0.000  |         | ns   |
| Hold time         | adr_b[9]     | after  | clk_b (rise) | 0.000  |         | ns   |
| Hold time         | d_a[0]       | after  | clk_a (rise) | 0.000  |         | ns   |
| Hold time         | d_a[1]       | after  | clk_a (rise) | 0.000  |         | ns   |
| Hold time         | d_a[2]       | after  | clk_a (rise) | 0.000  |         | ns   |
| Hold time         | d_a[3]       | after  | clk_a (rise) | 0.000  |         | ns   |
| Hold time         | d_a[4]       | after  | clk_a (rise) | 0.000  |         | ns   |
| Hold time         | d_a[5]       | after  | clk_a (rise) | 0.000  |         | ns   |
| Hold time         | d_a[6]       | after  | clk_a (rise) | 0.000  |         | ns   |
| Hold time         | d_a[7]       | after  | clk_a (rise) | 0.000  |         | ns   |
| Hold time         | d_b[0]       | after  | clk_b (rise) | 0.000  |         | ns   |
| Hold time         | d_b[1]       | after  | clk_b (rise) | 0.000  |         | ns   |
| Hold time         | d_b[2]       | after  | clk_b (rise) | 0.000  |         | ns   |
| Hold time         | d_b[3]       | after  | clk_b (rise) | 0.000  |         | ns   |
| Hold time         | d_b[4]       | after  | clk_b (rise) | 0.000  |         | ns   |
| Hold time         | d_b[5]       | after  | clk_b (rise) | 0.000  |         | ns   |
| Hold time         | d_b[6]       | after  | clk_b (rise) | 0.000  |         | ns   |
| Hold time         | d_b[7]       | after  | clk_b (rise) | 0.000  |         | ns   |
| Hold time         | we_a         | after  | clk_a (rise) | -0.353 |         | ns   |
| Hold time         | we_b         | after  | clk_b (rise) | -0.317 |         | ns   |
| Propagation delay | clk_a (rise) | to     | q_a[0]       | 1.063  | 3.154   | ns   |
| Propagation delay | clk_a (rise) | to     | q_a[1]       | 1.063  | 3.154   | ns   |
| Propagation delay | clk_a (rise) | to     | q_a[2]       | 1.063  | 3.154   | ns   |
| Propagation delay | clk_a (rise) | to     | q_a[3]       | 1.063  | 3.154   | ns   |
| Propagation delay | clk_a (rise) | to     | q_a[4]       | 1.063  | 3.154   | ns   |
| Propagation delay | clk_a (rise) | to     | q_a[5]       | 1.063  | 3.154   | ns   |
| Propagation delay | clk_a (rise) | to     | q_a[6]       | 1.063  | 3.154   | ns   |
| Propagation delay | clk_a (rise) | to     | q_a[7]       | 1.063  | 3.154   | ns   |
| Propagation delay | clk_b (rise) | to     | q_b[0]       | 1.057  | 3.139   | ns   |
| Propagation delay | clk_b (rise) | to     | q_b[1]       | 1.057  | 3.139   | ns   |
| Propagation delay | clk_b (rise) | to     | q_b[2]       | 1.057  | 3.139   | ns   |
| Propagation delay | clk_b (rise) | to     | q_b[3]       | 1.057  | 3.139   | ns   |
| Propagation delay | clk_b (rise) | to     | q_b[4]       | 1.057  | 3.139   | ns   |
| Propagation delay | clk_b (rise) | to     | q_b[5]       | 1.057  | 3.139   | ns   |
| Propagation delay | clk_b (rise) | to     | q_b[6]       | 1.057  | 3.139   | ns   |
| Propagation delay | clk_b (rise) | to     | q_b[7]       | 1.057  | 3.139   | ns   |
+-------------------+--------------+--------+--------------+--------+---------+------+


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