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[/] [sdcard_mass_storage_controller/] [trunk/] [backend/] [Actel/] [Block/] [versatile_fifo_dptam_dw/] [versatile_fifo_dptam_dw_usedLocations.pdc] - Rev 48
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# Actel Physical design constraints file
# To be used only for physical synthesis, or to be used when creating another User Block
# Version: 8.5 8.5.0.34
# Design Name: versatile_fifo_dptam_dw
# Input Netlist Format: edif
# Family: ProASIC3, Die: A3P1000, Package: 208 PQFP, Speed grade: STD
# Date generated: Tue Apr 21 10:24:26 2009
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