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[/] [sdhc-sc-core/] [trunk/] [grpMemory/] [unitSimpleDualPortedRam/] [src/] [SimpleDualPortedRam-Rtl-a.vhdl] - Rev 185
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-- SDHC-SC-Core -- Secure Digital High Capacity Self Configuring Core -- -- (C) Copyright 2010, Rainer Kastl -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions are met: -- * Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- * Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- * Neither the name of the <organization> nor the -- names of its contributors may be used to endorse or promote products -- derived from this software without specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY -- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- File : SimpleDualPortedRam-Rtl-a.vhdl -- Owner : Rainer Kastl -- Description : -- Links : -- architecture Rtl of SimpleDualPortedRam is signal tempq : std_logic_vector(31 downto 0); signal rdaddr, wraddr : unsigned(6 downto 0); begin Ram_inst: ENTITY work.CycSimpleDualPortedRam PORT map ( clock => iClk, data => std_logic_vector(iDataRw), rdaddress => std_logic_vector(rdaddr), wraddress => std_logic_vector(wraddr), wren => iWeRW, q => tempq ); oDataR <= std_ulogic_vector(tempq); rdaddr <= to_unsigned(iAddrR, rdaddr'length); wraddr <= to_unsigned(iAddrRW, wraddr'length); end architecture Rtl;