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-- SDHC-SC-Core -- Secure Digital High Capacity Self Configuring Core -- -- (C) Copyright 2010, Rainer Kastl -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions are met: -- * Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- * Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- * Neither the name of the <organization> nor the -- names of its contributors may be used to endorse or promote products -- derived from this software without specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY -- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- File : SdController-e.vhdl -- Owner : Rainer Kastl -- Description : Main FSM controlling Cmd and Data FSM, communicates with Wb -- Links : SD Spec 2.00 -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.Global.all; use work.Sd.all; use work.SdWb.all; entity SdController is generic ( gClkFrequency : natural := 25E6; gHighSpeedMode : boolean := true; gStartupTimeout : time := 1 ms; gReadTimeout : time := 100 ms; gWriteTimeout : time := 250 ms ); port ( iClk : in std_ulogic; -- rising edge iRstSync : in std_ulogic; oHighSpeed : out std_ulogic; -- SdCmd iSdCmd : in aSdCmdToController; oSdCmd : out aSdCmdFromController; -- SdData iSdData : in aSdDataToController; oSdData : out aSdDataFromController; -- SdWbSlave iSdWbSlave : in aSdWbSlaveToSdController; oSdWbSlave : out aSdControllerToSdWbSlave; -- Status oLedBank : out aLedBank ); begin assert (gStartupTimeout < gReadTimeout) report "gStartupTimeout has to be smaller than the read timeout" severity error; assert ((gHighSpeedMode = true and gClkFrequency >= 50E6) or gHighSpeedMode = false) report "High speed Mode needs at least 50 MHz clock" severity error; end entity SdController;