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-- SDHC-SC-Core
-- Secure Digital High Capacity Self Configuring Core
-- 
-- (C) Copyright 2010, Rainer Kastl
-- All rights reserved.
-- 
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--     * Redistributions of source code must retain the above copyright
--       notice, this list of conditions and the following disclaimer.
--     * Redistributions in binary form must reproduce the above copyright
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--     * Neither the name of the <organization> nor the
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--       derived from this software without specific prior written permission.
-- 
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS  "AS IS" AND
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-- 
-- File        : StrobeGen-Rtl-a.vhdl
-- Owner       : Rainer Kastl
-- Description : 
-- Links       : See EDS at FH Hagenberg
-- 
 
architecture Rtl of StrobeGen is
 
	constant max       : natural                           := gClkFrequency/(1 sec/ gStrobeCycleTime);
	constant cBitWidth : natural                           := LogDualis(max);  -- Bitwidth
	signal   Counter   : unsigned (cBitWidth - 1 downto 0) := (others => '0');
 
begin  -- architecture Rtl
 
	StateReg : process (iClk, inResetAsync) is
	begin  -- process StateReg
		if inResetAsync = cnActivated then  -- asynchronous reset (active low)
			Counter <= (others => '0');
			oStrobe <= cInactivated;
		elsif iClk'event and iClk = cActivated then  -- rising clock edge
			if (iRstSync = cActivated) then
				Counter <= (others => '0');
				oStrobe <= cInactivated;
 
			else
				Counter <= Counter + 1;
				if Counter < max - 1 then
					oStrobe <= cInactivated;
				else
					oStrobe <= cActivated;
					Counter <= TO_UNSIGNED(0, cBitWidth);
				end if;
			end if;
		end if;
	end process StateReg;
end architecture Rtl;