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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [core_sdr32_sim.log] - Rev 48
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Compiling with MODELSIM in core SDR_32BIT ModeModel Technology ModelSim ACTEL vlog 6.6d Compiler 2010.11 Nov 2 2010-- Compiling module tb_core-- Compiling module IS42VM16400K-- Compiling module mt48lc2m32b2-- Compiling module mt48lc8m8a2-- Compiling module sdrc_core-- Compiling module sdrc_bank_ctl-- Compiling module sdrc_bank_fsm-- Compiling module sdrc_bs_convert-- Compiling module sdrc_req_gen-- Compiling module sdrc_xfr_ctlTop level modules:tb_coreIS42VM16400Kmt48lc8m8a2#### Compile : PASSED###########################################Runing test programs######################################################################################### Running test 1: basic_test1Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl# 6.6d# vsim +basic_test1 -do run.do -c tb_core# // ModelSim ACTEL 6.6d Nov 2 2010# //# // Copyright 1991-2010 Mentor Graphics Corporation# // All Rights Reserved.# //# // THIS WORK CONTAINS TRADE SECRET AND# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS# // AND IS SUBJECT TO LICENSE TERMS.# //# Loading sv_std.std# Loading work.tb_core# Loading work.sdrc_core# Loading work.sdrc_req_gen# Loading work.sdrc_bank_ctl# Loading work.sdrc_bank_fsm# Loading work.sdrc_xfr_ctl# Loading work.sdrc_bs_convert# Loading work.mt48lc2m32b2# ** Warning: (vsim-3015) ../tb/tb_core.sv(199): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42).# Region: /tb_core/u_sdram32# do run.do# tb_core.u_sdram32 : at time 10157.0 ns AREF : Auto Refresh# tb_core.u_sdram32 : at time 10247.0 ns AREF : Auto Refresh# tb_core.u_sdram32 : at time 10337.0 ns AREF : Auto Refresh# tb_core.u_sdram32 : at time 10427.0 ns AREF : Auto Refresh# tb_core.u_sdram32 : at time 10517.0 ns AREF : Auto Refresh# tb_core.u_sdram32 : at time 10607.0 ns AREF : Auto Refresh# tb_core.u_sdram32 : at time 10697.0 ns AREF : Auto Refresh# tb_core.u_sdram32 : at time 10787.0 ns AREF : Auto Refresh# tb_core.u_sdram32 : at time 10877.0 ns AREF : Auto Refresh# tb_core.u_sdram32 : at time 10967.0 ns AREF : Auto Refresh# tb_core.u_sdram32 : at time 11057.0 ns AREF : Auto Refresh# tb_core.u_sdram32 : at time 11147.0 ns AREF : Auto Refresh# tb_core.u_sdram32 : at time 11237.0 ns AREF : Auto Refresh# tb_core.u_sdram32 : at time 11327.0 ns AREF : Auto Refresh# tb_core.u_sdram32 : at time 11417.0 ns AREF : Auto Refresh# tb_core.u_sdram32 : at time 11507.0 ns LMR : Load Mode Register# tb_core.u_sdram32 : CAS Latency = 3# tb_core.u_sdram32 : Burst Length = 8# tb_core.u_sdram32 : Burst Type = Sequential# tb_core.u_sdram32 : Write Burst Mode = Programmed Burst Length# ----------------------------------------# Case-3 Create a Page Cross Over# ----------------------------------------# Write Address: 00040ffc, Burst Size: 8# tb_core.u_sdram32 : at time 12647.0 ns ACT : Bank = 3 Row = 64# tb_core.u_sdram32 : at time 12677.0 ns WRITE: Bank = 3 Row = 64, Col = 255, Data = 12153524# Status: Burst-No: 0 Write Address: 00040ffc WriteData: 12153524# tb_core.u_sdram32 : at time 12687.0 ns BST : Burst Terminate# tb_core.u_sdram32 : at time 12697.0 ns ACT : Bank = 0 Row = 65# tb_core.u_sdram32 : at time 12727.0 ns WRITE: Bank = 0 Row = 65, Col = 0, Data = c0895e81# Status: Burst-No: 1 Write Address: 00040ffc WriteData: c0895e81# tb_core.u_sdram32 : at time 12737.0 ns WRITE: Bank = 0 Row = 65, Col = 1, Data = 8484d609# Status: Burst-No: 2 Write Address: 00040ffc WriteData: 8484d609# tb_core.u_sdram32 : at time 12747.0 ns WRITE: Bank = 0 Row = 65, Col = 2, Data = b1f05663# Status: Burst-No: 3 Write Address: 00040ffc WriteData: b1f05663# tb_core.u_sdram32 : at time 12757.0 ns WRITE: Bank = 0 Row = 65, Col = 3, Data = 06b97b0d# Status: Burst-No: 4 Write Address: 00040ffc WriteData: 06b97b0d# tb_core.u_sdram32 : at time 12767.0 ns WRITE: Bank = 0 Row = 65, Col = 4, Data = 46df998d# Status: Burst-No: 5 Write Address: 00040ffc WriteData: 46df998d# tb_core.u_sdram32 : at time 12777.0 ns WRITE: Bank = 0 Row = 65, Col = 5, Data = b2c28465# Status: Burst-No: 6 Write Address: 00040ffc WriteData: b2c28465# tb_core.u_sdram32 : at time 12787.0 ns WRITE: Bank = 0 Row = 65, Col = 6, Data = 89375212# Status: Burst-No: 7 Write Address: 00040ffc WriteData: 89375212# tb_core.u_sdram32 : at time 12797.0 ns BST : Burst Terminate# Write Address: 00400ff8, Burst Size: 15# tb_core.u_sdram32 : at time 12847.0 ns ACT : Bank = 3 Row = 1024# tb_core.u_sdram32 : at time 12877.0 ns WRITE: Bank = 3 Row = 1024, Col = 254, Data = 00f3e301# Status: Burst-No: 0 Write Address: 00400ff8 WriteData: 00f3e301# tb_core.u_sdram32 : at time 12887.0 ns ACT : Bank = 0 Row = 1025# tb_core.u_sdram32 : at time 12887.0 ns WRITE: Bank = 3 Row = 1024, Col = 255, Data = 06d7cd0d# Status: Burst-No: 1 Write Address: 00400ff8 WriteData: 06d7cd0d# tb_core.u_sdram32 : at time 12897.0 ns BST : Burst Terminate# tb_core.u_sdram32 : at time 12917.0 ns WRITE: Bank = 0 Row = 1025, Col = 0, Data = 3b23f176# Status: Burst-No: 2 Write Address: 00400ff8 WriteData: 3b23f176# tb_core.u_sdram32 : at time 12927.0 ns WRITE: Bank = 0 Row = 1025, Col = 1, Data = 1e8dcd3d# Status: Burst-No: 3 Write Address: 00400ff8 WriteData: 1e8dcd3d# tb_core.u_sdram32 : at time 12937.0 ns WRITE: Bank = 0 Row = 1025, Col = 2, Data = 76d457ed# Status: Burst-No: 4 Write Address: 00400ff8 WriteData: 76d457ed# tb_core.u_sdram32 : at time 12947.0 ns WRITE: Bank = 0 Row = 1025, Col = 3, Data = 462df78c# Status: Burst-No: 5 Write Address: 00400ff8 WriteData: 462df78c# tb_core.u_sdram32 : at time 12957.0 ns WRITE: Bank = 0 Row = 1025, Col = 4, Data = 7cfde9f9# Status: Burst-No: 6 Write Address: 00400ff8 WriteData: 7cfde9f9# tb_core.u_sdram32 : at time 12967.0 ns WRITE: Bank = 0 Row = 1025, Col = 5, Data = e33724c6# Status: Burst-No: 7 Write Address: 00400ff8 WriteData: e33724c6# tb_core.u_sdram32 : at time 12977.0 ns WRITE: Bank = 0 Row = 1025, Col = 6, Data = e2f784c5# Status: Burst-No: 8 Write Address: 00400ff8 WriteData: e2f784c5# tb_core.u_sdram32 : at time 12987.0 ns WRITE: Bank = 0 Row = 1025, Col = 7, Data = d513d2aa# Status: Burst-No: 9 Write Address: 00400ff8 WriteData: d513d2aa# tb_core.u_sdram32 : at time 12997.0 ns WRITE: Bank = 0 Row = 1025, Col = 8, Data = 72aff7e5# Status: Burst-No: 10 Write Address: 00400ff8 WriteData: 72aff7e5# tb_core.u_sdram32 : at time 13007.0 ns WRITE: Bank = 0 Row = 1025, Col = 9, Data = bbd27277# Status: Burst-No: 11 Write Address: 00400ff8 WriteData: bbd27277# tb_core.u_sdram32 : at time 13017.0 ns WRITE: Bank = 0 Row = 1025, Col = 10, Data = 8932d612# Status: Burst-No: 12 Write Address: 00400ff8 WriteData: 8932d612# tb_core.u_sdram32 : at time 13027.0 ns WRITE: Bank = 0 Row = 1025, Col = 11, Data = 47ecdb8f# Status: Burst-No: 13 Write Address: 00400ff8 WriteData: 47ecdb8f# tb_core.u_sdram32 : at time 13037.0 ns WRITE: Bank = 0 Row = 1025, Col = 12, Data = 793069f2# Status: Burst-No: 14 Write Address: 00400ff8 WriteData: 793069f2# tb_core.u_sdram32 : at time 13047.0 ns BST : Burst Terminate# tb_core.u_sdram32 : at time 13087.0 ns ACT : Bank = 3 Row = 64# tb_core.u_sdram32 : at time 13127.0 ns BST : Burst Terminate# tb_core.u_sdram32 : at time 13137.0 ns ACT : Bank = 0 Row = 65# tb_core.u_sdram32 : at time 13143.0 ns READ : Bank = 3 Row = 64, Col = 255, Data = 12153524# READ STATUS: Burst-No: 0 Addr: 00040ffc Rxd: 12153524# tb_core.u_sdram32 : at time 13193.0 ns READ : Bank = 0 Row = 65, Col = 0, Data = c0895e81# tb_core.u_sdram32 : at time 13203.0 ns READ : Bank = 0 Row = 65, Col = 1, Data = 8484d609# READ STATUS: Burst-No: 1 Addr: 00040ffe Rxd: c0895e81# tb_core.u_sdram32 : at time 13213.0 ns READ : Bank = 0 Row = 65, Col = 2, Data = b1f05663# READ STATUS: Burst-No: 2 Addr: 00041000 Rxd: 8484d609# tb_core.u_sdram32 : at time 13223.0 ns READ : Bank = 0 Row = 65, Col = 3, Data = 06b97b0d# READ STATUS: Burst-No: 3 Addr: 00041002 Rxd: b1f05663# tb_core.u_sdram32 : at time 13233.0 ns READ : Bank = 0 Row = 65, Col = 4, Data = 46df998d# tb_core.u_sdram32 : at time 13237.0 ns BST : Burst Terminate# READ STATUS: Burst-No: 4 Addr: 00041004 Rxd: 06b97b0d# tb_core.u_sdram32 : at time 13243.0 ns READ : Bank = 0 Row = 65, Col = 5, Data = b2c28465# READ STATUS: Burst-No: 5 Addr: 00041006 Rxd: 46df998d# tb_core.u_sdram32 : at time 13253.0 ns READ : Bank = 0 Row = 65, Col = 6, Data = 89375212# READ STATUS: Burst-No: 6 Addr: 00041008 Rxd: b2c28465# READ STATUS: Burst-No: 7 Addr: 0004100a Rxd: 89375212# tb_core.u_sdram32 : at time 13327.0 ns ACT : Bank = 3 Row = 1024# tb_core.u_sdram32 : at time 13367.0 ns ACT : Bank = 0 Row = 1025# tb_core.u_sdram32 : at time 13377.0 ns BST : Burst Terminate# tb_core.u_sdram32 : at time 13383.0 ns READ : Bank = 3 Row = 1024, Col = 254, Data = 00f3e301# tb_core.u_sdram32 : at time 13393.0 ns READ : Bank = 3 Row = 1024, Col = 255, Data = 06d7cd0d# READ STATUS: Burst-No: 0 Addr: 00400ff8 Rxd: 00f3e301# READ STATUS: Burst-No: 1 Addr: 00400ffa Rxd: 06d7cd0d# tb_core.u_sdram32 : at time 13423.0 ns READ : Bank = 0 Row = 1025, Col = 0, Data = 3b23f176# tb_core.u_sdram32 : at time 13433.0 ns READ : Bank = 0 Row = 1025, Col = 1, Data = 1e8dcd3d# READ STATUS: Burst-No: 2 Addr: 00400ffc Rxd: 3b23f176# tb_core.u_sdram32 : at time 13443.0 ns READ : Bank = 0 Row = 1025, Col = 2, Data = 76d457ed# READ STATUS: Burst-No: 3 Addr: 00400ffe Rxd: 1e8dcd3d# tb_core.u_sdram32 : at time 13453.0 ns READ : Bank = 0 Row = 1025, Col = 3, Data = 462df78c# READ STATUS: Burst-No: 4 Addr: 00401000 Rxd: 76d457ed# tb_core.u_sdram32 : at time 13463.0 ns READ : Bank = 0 Row = 1025, Col = 4, Data = 7cfde9f9# READ STATUS: Burst-No: 5 Addr: 00401002 Rxd: 462df78c# tb_core.u_sdram32 : at time 13473.0 ns READ : Bank = 0 Row = 1025, Col = 5, Data = e33724c6# READ STATUS: Burst-No: 6 Addr: 00401004 Rxd: 7cfde9f9# tb_core.u_sdram32 : at time 13483.0 ns READ : Bank = 0 Row = 1025, Col = 6, Data = e2f784c5# READ STATUS: Burst-No: 7 Addr: 00401006 Rxd: e33724c6# tb_core.u_sdram32 : at time 13493.0 ns READ : Bank = 0 Row = 1025, Col = 7, Data = d513d2aa# READ STATUS: Burst-No: 8 Addr: 00401008 Rxd: e2f784c5# tb_core.u_sdram32 : at time 13503.0 ns READ : Bank = 0 Row = 1025, Col = 8, Data = 72aff7e5# READ STATUS: Burst-No: 9 Addr: 0040100a Rxd: d513d2aa# tb_core.u_sdram32 : at time 13513.0 ns READ : Bank = 0 Row = 1025, Col = 9, Data = bbd27277# READ STATUS: Burst-No: 10 Addr: 0040100c Rxd: 72aff7e5# tb_core.u_sdram32 : at time 13523.0 ns READ : Bank = 0 Row = 1025, Col = 10, Data = 8932d612# tb_core.u_sdram32 : at time 13527.0 ns BST : Burst Terminate# READ STATUS: Burst-No: 11 Addr: 0040100e Rxd: bbd27277# tb_core.u_sdram32 : at time 13533.0 ns READ : Bank = 0 Row = 1025, Col = 11, Data = 47ecdb8f# READ STATUS: Burst-No: 12 Addr: 00401010 Rxd: 8932d612# tb_core.u_sdram32 : at time 13543.0 ns READ : Bank = 0 Row = 1025, Col = 12, Data = 793069f2# READ STATUS: Burst-No: 13 Addr: 00401012 Rxd: 47ecdb8f# READ STATUS: Burst-No: 14 Addr: 00401014 Rxd: 793069f2################################ STATUS: SDRAM Write/Read TEST PASSED################################ ** Note: $finish : ../tb/tb_core.sv(382)# Time: 23570 ns Iteration: 0 Instance: /tb_core### test 1: basic_test1 --> PASSED######################################################################################### Test Logstest 1: ../log/core_SDR_32BIT_basic_test1.log######################################################################################### Test Summary###### Failed 0 of 1 SDR_32BIT tests###########################################
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